Struct DirectCsr

#[repr(transparent)]
pub struct DirectCsr(pub u32);

Control and status for direct serial mode Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported.

Tuple Fields

0: u32

Implementations

impl DirectCsr

pub const fn en(&self) -> bool

Enable direct mode. In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when direct serial mode is enabled.

pub fn set_en(&mut self, val: bool)

Enable direct mode. In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when direct serial mode is enabled.

pub const fn busy(&self) -> bool

Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can’t halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.)

pub fn set_busy(&mut self, val: bool)

Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can’t halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.)

pub const fn assert_cs0n(&self) -> bool

When 1, assert (i.e. drive low) the CS0n chip select line. Note that this applies even when DIRECT_CSR_EN is 0.

pub fn set_assert_cs0n(&mut self, val: bool)

When 1, assert (i.e. drive low) the CS0n chip select line. Note that this applies even when DIRECT_CSR_EN is 0.

pub const fn assert_cs1n(&self) -> bool

When 1, assert (i.e. drive low) the CS1n chip select line. Note that this applies even when DIRECT_CSR_EN is 0.

pub fn set_assert_cs1n(&mut self, val: bool)

When 1, assert (i.e. drive low) the CS1n chip select line. Note that this applies even when DIRECT_CSR_EN is 0.

pub const fn auto_cs0n(&self) -> bool

When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set.

pub fn set_auto_cs0n(&mut self, val: bool)

When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set.

pub const fn auto_cs1n(&self) -> bool

When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set.

pub fn set_auto_cs1n(&mut self, val: bool)

When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set.

pub const fn txfull(&self) -> bool

When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored.

pub fn set_txfull(&mut self, val: bool)

When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored.

pub const fn txempty(&self) -> bool

When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes.

pub fn set_txempty(&mut self, val: bool)

When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes.

pub const fn txlevel(&self) -> u8

Current level of DIRECT_TX FIFO

pub fn set_txlevel(&mut self, val: u8)

Current level of DIRECT_TX FIFO

pub const fn rxempty(&self) -> bool

When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined.

pub fn set_rxempty(&mut self, val: bool)

When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined.

pub const fn rxfull(&self) -> bool

When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full.

pub fn set_rxfull(&mut self, val: bool)

When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full.

pub const fn rxlevel(&self) -> u8

Current level of DIRECT_RX FIFO

pub fn set_rxlevel(&mut self, val: u8)

Current level of DIRECT_RX FIFO

pub const fn clkdiv(&self) -> u8

Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte.

pub fn set_clkdiv(&mut self, val: u8)

Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte.

pub const fn rxdelay(&self) -> u8

Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)

pub fn set_rxdelay(&mut self, val: u8)

Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)

Trait Implementations

impl Clone for DirectCsr

fn clone(&self) -> DirectCsr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for DirectCsr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for DirectCsr

fn default() -> DirectCsr

Returns the “default value” for a type.

impl PartialEq for DirectCsr

fn eq(&self, other: &DirectCsr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for DirectCsr

impl Eq for DirectCsr

impl StructuralPartialEq for DirectCsr