Struct rp_pac::qmi::regs::Wfmt

#[repr(transparent)]
pub struct Wfmt(pub u32);

Write transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default.

Tuple Fields

0: u32

Implementations

impl Wfmt

pub const fn prefix_width(&self) -> PrefixWidth

The transfer width used for the command prefix, if any

pub fn set_prefix_width(&mut self, val: PrefixWidth)

The transfer width used for the command prefix, if any

pub const fn addr_width(&self) -> AddrWidth

The transfer width used for the address. The address phase always transfers 24 bits in total.

pub fn set_addr_width(&mut self, val: AddrWidth)

The transfer width used for the address. The address phase always transfers 24 bits in total.

pub const fn suffix_width(&self) -> SuffixWidth

The width used for the post-address command suffix, if any

pub fn set_suffix_width(&mut self, val: SuffixWidth)

The width used for the post-address command suffix, if any

pub const fn dummy_width(&self) -> DummyWidth

The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1…SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase.

pub fn set_dummy_width(&mut self, val: DummyWidth)

The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1…SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase.

pub const fn data_width(&self) -> DataWidth

The width used for the data transfer

pub fn set_data_width(&mut self, val: DataWidth)

The width used for the data transfer

pub const fn prefix_len(&self) -> PrefixLen

Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)

pub fn set_prefix_len(&mut self, val: PrefixLen)

Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)

pub const fn suffix_len(&self) -> SuffixLen

Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported.

pub fn set_suffix_len(&mut self, val: SuffixLen)

Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported.

pub const fn dummy_len(&self) -> DummyLen

Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)

pub fn set_dummy_len(&mut self, val: DummyLen)

Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)

pub const fn dtr(&self) -> bool

Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges.

pub fn set_dtr(&mut self, val: bool)

Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges.

Trait Implementations

impl Clone for Wfmt

fn clone(&self) -> Wfmt

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Wfmt

fn default() -> Wfmt

Returns the “default value” for a type.

impl PartialEq for Wfmt

fn eq(&self, other: &Wfmt) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Wfmt

impl Eq for Wfmt

impl StructuralPartialEq for Wfmt