Struct rp_pac::sha256::regs::Csr

#[repr(transparent)]
pub struct Csr(pub u32);

Control and status register

Tuple Fields

0: u32

Implementations

impl Csr

pub const fn start(&self) -> bool

Write 1 to prepare the SHA-256 core for a new checksum. The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers.

pub fn set_start(&mut self, val: bool)

Write 1 to prepare the SHA-256 core for a new checksum. The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers.

pub const fn wdata_rdy(&self) -> bool

If 1, the SHA-256 core is ready to accept more data through the WDATA register. After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest.

pub fn set_wdata_rdy(&mut self, val: bool)

If 1, the SHA-256 core is ready to accept more data through the WDATA register. After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest.

pub const fn sum_vld(&self) -> bool

If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed.

pub fn set_sum_vld(&mut self, val: bool)

If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed.

pub const fn err_wdata_not_rdy(&self) -> bool

Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear.

pub fn set_err_wdata_not_rdy(&mut self, val: bool)

Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear.

pub const fn dma_size(&self) -> DmaSize

Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core’s DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core’s message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block.

pub fn set_dma_size(&mut self, val: DmaSize)

Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core’s DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core’s message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block.

pub const fn bswap(&self) -> bool

Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. This block’s bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. However, when marshalling bytes into blocks, SHA expects that the first byte is the most significant in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around.

pub fn set_bswap(&mut self, val: bool)

Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. This block’s bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. However, when marshalling bytes into blocks, SHA expects that the first byte is the most significant in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around.

Trait Implementations

impl Clone for Csr

fn clone(&self) -> Csr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Csr

fn default() -> Csr

Returns the “default value” for a type.

impl PartialEq for Csr

fn eq(&self, other: &Csr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Csr

impl Eq for Csr

impl StructuralPartialEq for Csr