Struct rp_pac::sio::regs::Interp0ctrlLane0
source · #[repr(transparent)]pub struct Interp0ctrlLane0(pub u32);
Expand description
Control register for lane 0
Tuple Fields§
§0: u32
Implementations§
source§impl Interp0ctrlLane0
impl Interp0ctrlLane0
sourcepub const fn shift(&self) -> u8
pub const fn shift(&self) -> u8
Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised.
sourcepub fn set_shift(&mut self, val: u8)
pub fn set_shift(&mut self, val: u8)
Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised.
sourcepub const fn mask_lsb(&self) -> u8
pub const fn mask_lsb(&self) -> u8
The least-significant bit allowed to pass by the mask (inclusive)
sourcepub fn set_mask_lsb(&mut self, val: u8)
pub fn set_mask_lsb(&mut self, val: u8)
The least-significant bit allowed to pass by the mask (inclusive)
sourcepub const fn mask_msb(&self) -> u8
pub const fn mask_msb(&self) -> u8
The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out
sourcepub fn set_mask_msb(&mut self, val: u8)
pub fn set_mask_msb(&mut self, val: u8)
The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out
sourcepub const fn signed(&self) -> bool
pub const fn signed(&self) -> bool
If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
sourcepub fn set_signed(&mut self, val: bool)
pub fn set_signed(&mut self, val: bool)
If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
sourcepub const fn cross_input(&self) -> bool
pub const fn cross_input(&self) -> bool
If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
sourcepub fn set_cross_input(&mut self, val: bool)
pub fn set_cross_input(&mut self, val: bool)
If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
sourcepub const fn cross_result(&self) -> bool
pub const fn cross_result(&self) -> bool
If 1, feed the opposite lane’s result into this lane’s accumulator on POP.
sourcepub fn set_cross_result(&mut self, val: bool)
pub fn set_cross_result(&mut self, val: bool)
If 1, feed the opposite lane’s result into this lane’s accumulator on POP.
sourcepub const fn add_raw(&self) -> bool
pub const fn add_raw(&self) -> bool
If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
sourcepub fn set_add_raw(&mut self, val: bool)
pub fn set_add_raw(&mut self, val: bool)
If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
sourcepub const fn force_msb(&self) -> u8
pub const fn force_msb(&self) -> u8
ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM.
sourcepub fn set_force_msb(&mut self, val: u8)
pub fn set_force_msb(&mut self, val: u8)
ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM.
sourcepub const fn blend(&self) -> bool
pub const fn blend(&self) -> bool
Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.
sourcepub fn set_blend(&mut self, val: bool)
pub fn set_blend(&mut self, val: bool)
Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.
sourcepub fn set_overf0(&mut self, val: bool)
pub fn set_overf0(&mut self, val: bool)
Indicates if any masked-off MSBs in ACCUM0 are set.
sourcepub fn set_overf1(&mut self, val: bool)
pub fn set_overf1(&mut self, val: bool)
Indicates if any masked-off MSBs in ACCUM1 are set.
Trait Implementations§
source§impl Clone for Interp0ctrlLane0
impl Clone for Interp0ctrlLane0
source§fn clone(&self) -> Interp0ctrlLane0
fn clone(&self) -> Interp0ctrlLane0
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
. Read moresource§impl Default for Interp0ctrlLane0
impl Default for Interp0ctrlLane0
source§fn default() -> Interp0ctrlLane0
fn default() -> Interp0ctrlLane0
source§impl PartialEq for Interp0ctrlLane0
impl PartialEq for Interp0ctrlLane0
impl Copy for Interp0ctrlLane0
impl Eq for Interp0ctrlLane0
impl StructuralPartialEq for Interp0ctrlLane0
Auto Trait Implementations§
impl Freeze for Interp0ctrlLane0
impl RefUnwindSafe for Interp0ctrlLane0
impl Send for Interp0ctrlLane0
impl Sync for Interp0ctrlLane0
impl Unpin for Interp0ctrlLane0
impl UnwindSafe for Interp0ctrlLane0
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)