#[repr(transparent)]pub struct MtimeCtrl(pub u32);Expand description
Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores.
Tuple Fields§
§0: u32Implementations§
Source§impl MtimeCtrl
impl MtimeCtrl
Sourcepub const fn en(&self) -> bool
pub const fn en(&self) -> bool
Timer enable bit. When 0, the timer will not increment automatically.
Sourcepub fn set_en(&mut self, val: bool)
pub fn set_en(&mut self, val: bool)
Timer enable bit. When 0, the timer will not increment automatically.
Sourcepub const fn fullspeed(&self) -> bool
pub const fn fullspeed(&self) -> bool
If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input.
Sourcepub fn set_fullspeed(&mut self, val: bool)
pub fn set_fullspeed(&mut self, val: bool)
If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input.
Sourcepub const fn dbgpause_core0(&self) -> bool
pub const fn dbgpause_core0(&self) -> bool
If 1, the timer pauses when core 0 is in the debug halt state.
Sourcepub fn set_dbgpause_core0(&mut self, val: bool)
pub fn set_dbgpause_core0(&mut self, val: bool)
If 1, the timer pauses when core 0 is in the debug halt state.
Sourcepub const fn dbgpause_core1(&self) -> bool
pub const fn dbgpause_core1(&self) -> bool
If 1, the timer pauses when core 1 is in the debug halt state.
Sourcepub fn set_dbgpause_core1(&mut self, val: bool)
pub fn set_dbgpause_core1(&mut self, val: bool)
If 1, the timer pauses when core 1 is in the debug halt state.