#[repr(transparent)]pub struct RiscvSoftirq(pub u32);
Expand description
Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect.
Tuple Fields§
§0: u32
Implementations§
Source§impl RiscvSoftirq
impl RiscvSoftirq
Sourcepub const fn core0_set(&self) -> bool
pub const fn core0_set(&self) -> bool
Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag.
Sourcepub fn set_core0_set(&mut self, val: bool)
pub fn set_core0_set(&mut self, val: bool)
Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag.
Sourcepub const fn core1_set(&self) -> bool
pub const fn core1_set(&self) -> bool
Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag.
Sourcepub fn set_core1_set(&mut self, val: bool)
pub fn set_core1_set(&mut self, val: bool)
Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag.
Sourcepub const fn core0_clr(&self) -> bool
pub const fn core0_clr(&self) -> bool
Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag.
Sourcepub fn set_core0_clr(&mut self, val: bool)
pub fn set_core0_clr(&mut self, val: bool)
Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag.
Sourcepub const fn core1_clr(&self) -> bool
pub const fn core1_clr(&self) -> bool
Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag.
Sourcepub fn set_core1_clr(&mut self, val: bool)
pub fn set_core1_clr(&mut self, val: bool)
Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag.
Trait Implementations§
Source§impl Clone for RiscvSoftirq
impl Clone for RiscvSoftirq
Source§fn clone(&self) -> RiscvSoftirq
fn clone(&self) -> RiscvSoftirq
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
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