Struct rp_pac::sio::regs::RiscvSoftirq
source · #[repr(transparent)]pub struct RiscvSoftirq(pub u32);
Expand description
Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect.
Tuple Fields§
§0: u32
Implementations§
source§impl RiscvSoftirq
impl RiscvSoftirq
sourcepub const fn core0_set(&self) -> bool
pub const fn core0_set(&self) -> bool
Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag.
sourcepub fn set_core0_set(&mut self, val: bool)
pub fn set_core0_set(&mut self, val: bool)
Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag.
sourcepub const fn core1_set(&self) -> bool
pub const fn core1_set(&self) -> bool
Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag.
sourcepub fn set_core1_set(&mut self, val: bool)
pub fn set_core1_set(&mut self, val: bool)
Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag.
sourcepub const fn core0_clr(&self) -> bool
pub const fn core0_clr(&self) -> bool
Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag.
sourcepub fn set_core0_clr(&mut self, val: bool)
pub fn set_core0_clr(&mut self, val: bool)
Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag.
sourcepub const fn core1_clr(&self) -> bool
pub const fn core1_clr(&self) -> bool
Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag.
sourcepub fn set_core1_clr(&mut self, val: bool)
pub fn set_core1_clr(&mut self, val: bool)
Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag.
Trait Implementations§
source§impl Clone for RiscvSoftirq
impl Clone for RiscvSoftirq
source§fn clone(&self) -> RiscvSoftirq
fn clone(&self) -> RiscvSoftirq
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
. Read moresource§impl Default for RiscvSoftirq
impl Default for RiscvSoftirq
source§fn default() -> RiscvSoftirq
fn default() -> RiscvSoftirq
source§impl PartialEq for RiscvSoftirq
impl PartialEq for RiscvSoftirq
impl Copy for RiscvSoftirq
impl Eq for RiscvSoftirq
impl StructuralPartialEq for RiscvSoftirq
Auto Trait Implementations§
impl Freeze for RiscvSoftirq
impl RefUnwindSafe for RiscvSoftirq
impl Send for RiscvSoftirq
impl Sync for RiscvSoftirq
impl Unpin for RiscvSoftirq
impl UnwindSafe for RiscvSoftirq
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)