#[repr(transparent)]pub struct Imsc(pub u32);
Expand description
Interrupt mask set or clear register, SSPIMSC on page 3-9
Tuple Fields§
§0: u32
Implementations§
Source§impl Imsc
impl Imsc
Sourcepub const fn rorim(&self) -> bool
pub const fn rorim(&self) -> bool
Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.
Sourcepub fn set_rorim(&mut self, val: bool)
pub fn set_rorim(&mut self, val: bool)
Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.
Sourcepub const fn rtim(&self) -> bool
pub const fn rtim(&self) -> bool
Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.
Sourcepub fn set_rtim(&mut self, val: bool)
pub fn set_rtim(&mut self, val: bool)
Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.
Sourcepub const fn rxim(&self) -> bool
pub const fn rxim(&self) -> bool
Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.
Sourcepub fn set_rxim(&mut self, val: bool)
pub fn set_rxim(&mut self, val: bool)
Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.