Struct rp_pac::xip_aux::regs::QmiDirectTx

#[repr(transparent)]
pub struct QmiDirectTx(pub u32);

Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX)

Tuple Fields

0: u32

Implementations

impl QmiDirectTx

pub const fn data(&self) -> u16

Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first.

pub fn set_data(&mut self, val: u16)

Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first.

pub const fn iwidth(&self) -> Iwidth

Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely.

pub fn set_iwidth(&mut self, val: Iwidth)

Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely.

pub const fn dwidth(&self) -> bool

Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely.

pub fn set_dwidth(&mut self, val: bool)

Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely.

pub const fn oe(&self) -> bool

Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer.

pub fn set_oe(&mut self, val: bool)

Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer.

pub const fn nopush(&self) -> bool

Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer.

pub fn set_nopush(&mut self, val: bool)

Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer.

Trait Implementations

impl Clone for QmiDirectTx

fn clone(&self) -> QmiDirectTx

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for QmiDirectTx

fn default() -> QmiDirectTx

Returns the “default value” for a type.

impl PartialEq for QmiDirectTx

fn eq(&self, other: &QmiDirectTx) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for QmiDirectTx

impl Eq for QmiDirectTx

impl StructuralPartialEq for QmiDirectTx