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embassy-mspm0

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embassy_mspm0

Struct Peripherals

Source 
pub struct Peripherals {
Show 129 fields
    pub ADC0: Peri<'static, ADC0>,
    pub ADC0_0: Peri<'static, ADC0_0>,
    pub ADC0_1: Peri<'static, ADC0_1>,
    pub ADC0_12: Peri<'static, ADC0_12>,
    pub ADC0_13: Peri<'static, ADC0_13>,
    pub ADC0_14: Peri<'static, ADC0_14>,
    pub ADC0_15: Peri<'static, ADC0_15>,
    pub ADC0_16: Peri<'static, ADC0_16>,
    pub ADC0_17: Peri<'static, ADC0_17>,
    pub ADC0_18: Peri<'static, ADC0_18>,
    pub ADC0_2: Peri<'static, ADC0_2>,
    pub ADC0_22: Peri<'static, ADC0_22>,
    pub ADC0_25: Peri<'static, ADC0_25>,
    pub ADC0_26: Peri<'static, ADC0_26>,
    pub ADC0_3: Peri<'static, ADC0_3>,
    pub ADC0_4: Peri<'static, ADC0_4>,
    pub ADC0_7: Peri<'static, ADC0_7>,
    pub ADC0_8: Peri<'static, ADC0_8>,
    pub COMP0: Peri<'static, COMP0>,
    pub COMP0_DAC_OUT: Peri<'static, COMP0_DAC_OUT>,
    pub COMP0_IN0_N: Peri<'static, COMP0_IN0_N>,
    pub COMP0_IN0_P: Peri<'static, COMP0_IN0_P>,
    pub COMP0_IN1_N: Peri<'static, COMP0_IN1_N>,
    pub COMP0_IN1_P: Peri<'static, COMP0_IN1_P>,
    pub COMP0_IN2_N: Peri<'static, COMP0_IN2_N>,
    pub COMP0_IN2_P: Peri<'static, COMP0_IN2_P>,
    pub COMP0_IN3_P: Peri<'static, COMP0_IN3_P>,
    pub COMP0_OUT: Peri<'static, COMP0_OUT>,
    pub CRC: Peri<'static, CRC>,
    pub DEBUGSS: Peri<'static, DEBUGSS>,
    pub DEBUGSS_SWCLK: Peri<'static, DEBUGSS_SWCLK>,
    pub DEBUGSS_SWDIO: Peri<'static, DEBUGSS_SWDIO>,
    pub DMA_CH0: Peri<'static, DMA_CH0>,
    pub DMA_CH1: Peri<'static, DMA_CH1>,
    pub DMA_CH2: Peri<'static, DMA_CH2>,
    pub EVENT: Peri<'static, EVENT>,
    pub FLASHCTL: Peri<'static, FLASHCTL>,
    pub I2C0: Peri<'static, I2C0>,
    pub I2C0_SCL: Peri<'static, I2C0_SCL>,
    pub I2C0_SDA: Peri<'static, I2C0_SDA>,
    pub I2C1: Peri<'static, I2C1>,
    pub I2C1_SCL: Peri<'static, I2C1_SCL>,
    pub I2C1_SDA: Peri<'static, I2C1_SDA>,
    pub LFSS: Peri<'static, LFSS>,
    pub LFSS_RTC_OUT: Peri<'static, LFSS_RTC_OUT>,
    pub PA0: Peri<'static, PA0>,
    pub PA1: Peri<'static, PA1>,
    pub PA10: Peri<'static, PA10>,
    pub PA11: Peri<'static, PA11>,
    pub PA12: Peri<'static, PA12>,
    pub PA13: Peri<'static, PA13>,
    pub PA14: Peri<'static, PA14>,
    pub PA15: Peri<'static, PA15>,
    pub PA16: Peri<'static, PA16>,
    pub PA17: Peri<'static, PA17>,
    pub PA18: Peri<'static, PA18>,
    pub PA19: Peri<'static, PA19>,
    pub PA2: Peri<'static, PA2>,
    pub PA20: Peri<'static, PA20>,
    pub PA21: Peri<'static, PA21>,
    pub PA22: Peri<'static, PA22>,
    pub PA23: Peri<'static, PA23>,
    pub PA24: Peri<'static, PA24>,
    pub PA25: Peri<'static, PA25>,
    pub PA26: Peri<'static, PA26>,
    pub PA27: Peri<'static, PA27>,
    pub PA3: Peri<'static, PA3>,
    pub PA30: Peri<'static, PA30>,
    pub PA4: Peri<'static, PA4>,
    pub PA5: Peri<'static, PA5>,
    pub PA6: Peri<'static, PA6>,
    pub PA7: Peri<'static, PA7>,
    pub PA8: Peri<'static, PA8>,
    pub PA9: Peri<'static, PA9>,
    pub SPI0: Peri<'static, SPI0>,
    pub SPI0_CS0: Peri<'static, SPI0_CS0>,
    pub SPI0_CS1_POCI1: Peri<'static, SPI0_CS1_POCI1>,
    pub SPI0_CS2_POCI2: Peri<'static, SPI0_CS2_POCI2>,
    pub SPI0_CS3_CD_POCI3: Peri<'static, SPI0_CS3_CD_POCI3>,
    pub SPI0_PICO: Peri<'static, SPI0_PICO>,
    pub SPI0_POCI: Peri<'static, SPI0_POCI>,
    pub SPI0_SCLK: Peri<'static, SPI0_SCLK>,
    pub TIMA0: Peri<'static, TIMA0>,
    pub TIMA0_CCP0: Peri<'static, TIMA0_CCP0>,
    pub TIMA0_CCP0_CMPL: Peri<'static, TIMA0_CCP0_CMPL>,
    pub TIMA0_CCP1: Peri<'static, TIMA0_CCP1>,
    pub TIMA0_CCP1_CMPL: Peri<'static, TIMA0_CCP1_CMPL>,
    pub TIMA0_CCP2: Peri<'static, TIMA0_CCP2>,
    pub TIMA0_CCP2_CMPL: Peri<'static, TIMA0_CCP2_CMPL>,
    pub TIMA0_CCP3: Peri<'static, TIMA0_CCP3>,
    pub TIMA0_CCP3_CMPL: Peri<'static, TIMA0_CCP3_CMPL>,
    pub TIMA0_FAULT0: Peri<'static, TIMA0_FAULT0>,
    pub TIMA0_FAULT1: Peri<'static, TIMA0_FAULT1>,
    pub TIMA0_FAULT2: Peri<'static, TIMA0_FAULT2>,
    pub TIMG1: Peri<'static, TIMG1>,
    pub TIMG14: Peri<'static, TIMG14>,
    pub TIMG14_CCP0: Peri<'static, TIMG14_CCP0>,
    pub TIMG14_CCP1: Peri<'static, TIMG14_CCP1>,
    pub TIMG14_CCP2: Peri<'static, TIMG14_CCP2>,
    pub TIMG14_CCP3: Peri<'static, TIMG14_CCP3>,
    pub TIMG1_CCP0: Peri<'static, TIMG1_CCP0>,
    pub TIMG1_CCP1: Peri<'static, TIMG1_CCP1>,
    pub TIMG2: Peri<'static, TIMG2>,
    pub TIMG2_CCP0: Peri<'static, TIMG2_CCP0>,
    pub TIMG2_CCP1: Peri<'static, TIMG2_CCP1>,
    pub TIMG8: Peri<'static, TIMG8>,
    pub TIMG8_CCP0: Peri<'static, TIMG8_CCP0>,
    pub TIMG8_CCP1: Peri<'static, TIMG8_CCP1>,
    pub TIMG8_IDX: Peri<'static, TIMG8_IDX>,
    pub UART0: Peri<'static, UART0>,
    pub UART0_CTS: Peri<'static, UART0_CTS>,
    pub UART0_RTS: Peri<'static, UART0_RTS>,
    pub UART0_RX: Peri<'static, UART0_RX>,
    pub UART0_TX: Peri<'static, UART0_TX>,
    pub UART1: Peri<'static, UART1>,
    pub UART1_CTS: Peri<'static, UART1_CTS>,
    pub UART1_RTS: Peri<'static, UART1_RTS>,
    pub UART1_RX: Peri<'static, UART1_RX>,
    pub UART1_TX: Peri<'static, UART1_TX>,
    pub UART2: Peri<'static, UART2>,
    pub UART2_CTS: Peri<'static, UART2_CTS>,
    pub UART2_RTS: Peri<'static, UART2_RTS>,
    pub UART2_RX: Peri<'static, UART2_RX>,
    pub UART2_TX: Peri<'static, UART2_TX>,
    pub VREF: Peri<'static, VREF>,
    pub VREF_N: Peri<'static, VREF_N>,
    pub VREF_P: Peri<'static, VREF_P>,
    pub WUC: Peri<'static, WUC>,
    pub WWDT0: Peri<'static, WWDT0>,

}
Expand description

Struct containing all the peripheral singletons.

To obtain the peripherals, you must initialize the HAL, by calling crate::init.

Fields§

§ADC0: Peri<'static, ADC0>

ADC0 peripheral

§ADC0_0: Peri<'static, ADC0_0>

ADC0_0 peripheral

§ADC0_1: Peri<'static, ADC0_1>

ADC0_1 peripheral

§ADC0_12: Peri<'static, ADC0_12>

ADC0_12 peripheral

§ADC0_13: Peri<'static, ADC0_13>

ADC0_13 peripheral

§ADC0_14: Peri<'static, ADC0_14>

ADC0_14 peripheral

§ADC0_15: Peri<'static, ADC0_15>

ADC0_15 peripheral

§ADC0_16: Peri<'static, ADC0_16>

ADC0_16 peripheral

§ADC0_17: Peri<'static, ADC0_17>

ADC0_17 peripheral

§ADC0_18: Peri<'static, ADC0_18>

ADC0_18 peripheral

§ADC0_2: Peri<'static, ADC0_2>

ADC0_2 peripheral

§ADC0_22: Peri<'static, ADC0_22>

ADC0_22 peripheral

§ADC0_25: Peri<'static, ADC0_25>

ADC0_25 peripheral

§ADC0_26: Peri<'static, ADC0_26>

ADC0_26 peripheral

§ADC0_3: Peri<'static, ADC0_3>

ADC0_3 peripheral

§ADC0_4: Peri<'static, ADC0_4>

ADC0_4 peripheral

§ADC0_7: Peri<'static, ADC0_7>

ADC0_7 peripheral

§ADC0_8: Peri<'static, ADC0_8>

ADC0_8 peripheral

§COMP0: Peri<'static, COMP0>

COMP0 peripheral

§COMP0_DAC_OUT: Peri<'static, COMP0_DAC_OUT>

COMP0_DAC_OUT peripheral

§COMP0_IN0_N: Peri<'static, COMP0_IN0_N>

COMP0_IN0_N peripheral

§COMP0_IN0_P: Peri<'static, COMP0_IN0_P>

COMP0_IN0_P peripheral

§COMP0_IN1_N: Peri<'static, COMP0_IN1_N>

COMP0_IN1_N peripheral

§COMP0_IN1_P: Peri<'static, COMP0_IN1_P>

COMP0_IN1_P peripheral

§COMP0_IN2_N: Peri<'static, COMP0_IN2_N>

COMP0_IN2_N peripheral

§COMP0_IN2_P: Peri<'static, COMP0_IN2_P>

COMP0_IN2_P peripheral

§COMP0_IN3_P: Peri<'static, COMP0_IN3_P>

COMP0_IN3_P peripheral

§COMP0_OUT: Peri<'static, COMP0_OUT>

COMP0_OUT peripheral

§CRC: Peri<'static, CRC>

CRC peripheral

§DEBUGSS: Peri<'static, DEBUGSS>

DEBUGSS peripheral

§DEBUGSS_SWCLK: Peri<'static, DEBUGSS_SWCLK>

DEBUGSS_SWCLK peripheral

§DEBUGSS_SWDIO: Peri<'static, DEBUGSS_SWDIO>

DEBUGSS_SWDIO peripheral

§DMA_CH0: Peri<'static, DMA_CH0>

DMA_CH0 peripheral

§DMA_CH1: Peri<'static, DMA_CH1>

DMA_CH1 peripheral

§DMA_CH2: Peri<'static, DMA_CH2>

DMA_CH2 peripheral

§EVENT: Peri<'static, EVENT>

EVENT peripheral

§FLASHCTL: Peri<'static, FLASHCTL>

FLASHCTL peripheral

§I2C0: Peri<'static, I2C0>

I2C0 peripheral

§I2C0_SCL: Peri<'static, I2C0_SCL>

I2C0_SCL peripheral

§I2C0_SDA: Peri<'static, I2C0_SDA>

I2C0_SDA peripheral

§I2C1: Peri<'static, I2C1>

I2C1 peripheral

§I2C1_SCL: Peri<'static, I2C1_SCL>

I2C1_SCL peripheral

§I2C1_SDA: Peri<'static, I2C1_SDA>

I2C1_SDA peripheral

§LFSS: Peri<'static, LFSS>

LFSS peripheral

§LFSS_RTC_OUT: Peri<'static, LFSS_RTC_OUT>

LFSS_RTC_OUT peripheral

§PA0: Peri<'static, PA0>

PA0 peripheral

§PA1: Peri<'static, PA1>

PA1 peripheral

§PA10: Peri<'static, PA10>

PA10 peripheral

§PA11: Peri<'static, PA11>

PA11 peripheral

§PA12: Peri<'static, PA12>

PA12 peripheral

§PA13: Peri<'static, PA13>

PA13 peripheral

§PA14: Peri<'static, PA14>

PA14 peripheral

§PA15: Peri<'static, PA15>

PA15 peripheral

§PA16: Peri<'static, PA16>

PA16 peripheral

§PA17: Peri<'static, PA17>

PA17 peripheral

§PA18: Peri<'static, PA18>

PA18 peripheral

§PA19: Peri<'static, PA19>

PA19 peripheral

§PA2: Peri<'static, PA2>

PA2 peripheral

§PA20: Peri<'static, PA20>

PA20 peripheral

§PA21: Peri<'static, PA21>

PA21 peripheral

§PA22: Peri<'static, PA22>

PA22 peripheral

§PA23: Peri<'static, PA23>

PA23 peripheral

§PA24: Peri<'static, PA24>

PA24 peripheral

§PA25: Peri<'static, PA25>

PA25 peripheral

§PA26: Peri<'static, PA26>

PA26 peripheral

§PA27: Peri<'static, PA27>

PA27 peripheral

§PA3: Peri<'static, PA3>

PA3 peripheral

§PA30: Peri<'static, PA30>

PA30 peripheral

§PA4: Peri<'static, PA4>

PA4 peripheral

§PA5: Peri<'static, PA5>

PA5 peripheral

§PA6: Peri<'static, PA6>

PA6 peripheral

§PA7: Peri<'static, PA7>

PA7 peripheral

§PA8: Peri<'static, PA8>

PA8 peripheral

§PA9: Peri<'static, PA9>

PA9 peripheral

§SPI0: Peri<'static, SPI0>

SPI0 peripheral

§SPI0_CS0: Peri<'static, SPI0_CS0>

SPI0_CS0 peripheral

§SPI0_CS1_POCI1: Peri<'static, SPI0_CS1_POCI1>

SPI0_CS1_POCI1 peripheral

§SPI0_CS2_POCI2: Peri<'static, SPI0_CS2_POCI2>

SPI0_CS2_POCI2 peripheral

§SPI0_CS3_CD_POCI3: Peri<'static, SPI0_CS3_CD_POCI3>

SPI0_CS3_CD_POCI3 peripheral

§SPI0_PICO: Peri<'static, SPI0_PICO>

SPI0_PICO peripheral

§SPI0_POCI: Peri<'static, SPI0_POCI>

SPI0_POCI peripheral

§SPI0_SCLK: Peri<'static, SPI0_SCLK>

SPI0_SCLK peripheral

§TIMA0: Peri<'static, TIMA0>

TIMA0 peripheral

§TIMA0_CCP0: Peri<'static, TIMA0_CCP0>

TIMA0_CCP0 peripheral

§TIMA0_CCP0_CMPL: Peri<'static, TIMA0_CCP0_CMPL>

TIMA0_CCP0_CMPL peripheral

§TIMA0_CCP1: Peri<'static, TIMA0_CCP1>

TIMA0_CCP1 peripheral

§TIMA0_CCP1_CMPL: Peri<'static, TIMA0_CCP1_CMPL>

TIMA0_CCP1_CMPL peripheral

§TIMA0_CCP2: Peri<'static, TIMA0_CCP2>

TIMA0_CCP2 peripheral

§TIMA0_CCP2_CMPL: Peri<'static, TIMA0_CCP2_CMPL>

TIMA0_CCP2_CMPL peripheral

§TIMA0_CCP3: Peri<'static, TIMA0_CCP3>

TIMA0_CCP3 peripheral

§TIMA0_CCP3_CMPL: Peri<'static, TIMA0_CCP3_CMPL>

TIMA0_CCP3_CMPL peripheral

§TIMA0_FAULT0: Peri<'static, TIMA0_FAULT0>

TIMA0_FAULT0 peripheral

§TIMA0_FAULT1: Peri<'static, TIMA0_FAULT1>

TIMA0_FAULT1 peripheral

§TIMA0_FAULT2: Peri<'static, TIMA0_FAULT2>

TIMA0_FAULT2 peripheral

§TIMG1: Peri<'static, TIMG1>

TIMG1 peripheral

§TIMG14: Peri<'static, TIMG14>

TIMG14 peripheral

§TIMG14_CCP0: Peri<'static, TIMG14_CCP0>

TIMG14_CCP0 peripheral

§TIMG14_CCP1: Peri<'static, TIMG14_CCP1>

TIMG14_CCP1 peripheral

§TIMG14_CCP2: Peri<'static, TIMG14_CCP2>

TIMG14_CCP2 peripheral

§TIMG14_CCP3: Peri<'static, TIMG14_CCP3>

TIMG14_CCP3 peripheral

§TIMG1_CCP0: Peri<'static, TIMG1_CCP0>

TIMG1_CCP0 peripheral

§TIMG1_CCP1: Peri<'static, TIMG1_CCP1>

TIMG1_CCP1 peripheral

§TIMG2: Peri<'static, TIMG2>

TIMG2 peripheral

§TIMG2_CCP0: Peri<'static, TIMG2_CCP0>

TIMG2_CCP0 peripheral

§TIMG2_CCP1: Peri<'static, TIMG2_CCP1>

TIMG2_CCP1 peripheral

§TIMG8: Peri<'static, TIMG8>

TIMG8 peripheral

§TIMG8_CCP0: Peri<'static, TIMG8_CCP0>

TIMG8_CCP0 peripheral

§TIMG8_CCP1: Peri<'static, TIMG8_CCP1>

TIMG8_CCP1 peripheral

§TIMG8_IDX: Peri<'static, TIMG8_IDX>

TIMG8_IDX peripheral

§UART0: Peri<'static, UART0>

UART0 peripheral

§UART0_CTS: Peri<'static, UART0_CTS>

UART0_CTS peripheral

§UART0_RTS: Peri<'static, UART0_RTS>

UART0_RTS peripheral

§UART0_RX: Peri<'static, UART0_RX>

UART0_RX peripheral

§UART0_TX: Peri<'static, UART0_TX>

UART0_TX peripheral

§UART1: Peri<'static, UART1>

UART1 peripheral

§UART1_CTS: Peri<'static, UART1_CTS>

UART1_CTS peripheral

§UART1_RTS: Peri<'static, UART1_RTS>

UART1_RTS peripheral

§UART1_RX: Peri<'static, UART1_RX>

UART1_RX peripheral

§UART1_TX: Peri<'static, UART1_TX>

UART1_TX peripheral

§UART2: Peri<'static, UART2>

UART2 peripheral

§UART2_CTS: Peri<'static, UART2_CTS>

UART2_CTS peripheral

§UART2_RTS: Peri<'static, UART2_RTS>

UART2_RTS peripheral

§UART2_RX: Peri<'static, UART2_RX>

UART2_RX peripheral

§UART2_TX: Peri<'static, UART2_TX>

UART2_TX peripheral

§VREF: Peri<'static, VREF>

VREF peripheral

§VREF_N: Peri<'static, VREF_N>

VREF_N peripheral

§VREF_P: Peri<'static, VREF_P>

VREF_P peripheral

§WUC: Peri<'static, WUC>

WUC peripheral

§WWDT0: Peri<'static, WWDT0>

WWDT0 peripheral

Implementations§

Source§

impl Peripherals

Source

pub unsafe fn steal() -> Self

Unsafely create an instance of this peripheral out of thin air.

§Safety

You must ensure that you’re only using one instance of this type at a time.

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Casts the value.
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Performs the conversion.
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Performs the conversion.
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Casts the value.
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Casts the value.
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type Output = T

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fn saturating_as<Dst>(self) -> Dst
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fn saturating_cast_from(src: Src) -> Dst

Casts the value.
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Casts the value.
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Casts the value.
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where T: WrappingCast<Dst>,

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Casts the value.