Enum Interrupt
pub enum Interrupt {
Show 49 variants
WWDG = 0,
PVD = 1,
TAMP_STAMP = 2,
RTC_WKUP = 3,
FLASH = 4,
RCC = 5,
EXTI0 = 6,
EXTI1 = 7,
EXTI2 = 8,
EXTI3 = 9,
EXTI4 = 10,
DMA1_STREAM0 = 11,
DMA1_STREAM1 = 12,
DMA1_STREAM2 = 13,
DMA1_STREAM3 = 14,
DMA1_STREAM4 = 15,
DMA1_STREAM5 = 16,
DMA1_STREAM6 = 17,
ADC = 18,
EXTI9_5 = 23,
TIM1_BRK_TIM9 = 24,
TIM1_UP = 25,
TIM1_TRG_COM_TIM11 = 26,
TIM1_CC = 27,
I2C1_EV = 31,
I2C1_ER = 32,
I2C2_EV = 33,
I2C2_ER = 34,
SPI1 = 35,
USART1 = 37,
USART2 = 38,
EXTI15_10 = 40,
RTC_ALARM = 41,
DMA1_STREAM7 = 47,
TIM5 = 50,
TIM6_DAC = 54,
DMA2_STREAM0 = 56,
DMA2_STREAM1 = 57,
DMA2_STREAM2 = 58,
DMA2_STREAM3 = 59,
DMA2_STREAM4 = 60,
DMA2_STREAM5 = 68,
DMA2_STREAM6 = 69,
DMA2_STREAM7 = 70,
RNG = 80,
FPU = 81,
FMPI2C1_EV = 95,
FMPI2C1_ER = 96,
LPTIM1 = 97,
}
Variants§
WWDG = 0
0 - WWDG
PVD = 1
1 - PVD
TAMP_STAMP = 2
2 - TAMP_STAMP
RTC_WKUP = 3
3 - RTC_WKUP
FLASH = 4
4 - FLASH
RCC = 5
5 - RCC
EXTI0 = 6
6 - EXTI0
EXTI1 = 7
7 - EXTI1
EXTI2 = 8
8 - EXTI2
EXTI3 = 9
9 - EXTI3
EXTI4 = 10
10 - EXTI4
DMA1_STREAM0 = 11
11 - DMA1_STREAM0
DMA1_STREAM1 = 12
12 - DMA1_STREAM1
DMA1_STREAM2 = 13
13 - DMA1_STREAM2
DMA1_STREAM3 = 14
14 - DMA1_STREAM3
DMA1_STREAM4 = 15
15 - DMA1_STREAM4
DMA1_STREAM5 = 16
16 - DMA1_STREAM5
DMA1_STREAM6 = 17
17 - DMA1_STREAM6
ADC = 18
18 - ADC
EXTI9_5 = 23
23 - EXTI9_5
TIM1_BRK_TIM9 = 24
24 - TIM1_BRK_TIM9
TIM1_UP = 25
25 - TIM1_UP
TIM1_TRG_COM_TIM11 = 26
26 - TIM1_TRG_COM_TIM11
TIM1_CC = 27
27 - TIM1_CC
I2C1_EV = 31
31 - I2C1_EV
I2C1_ER = 32
32 - I2C1_ER
I2C2_EV = 33
33 - I2C2_EV
I2C2_ER = 34
34 - I2C2_ER
SPI1 = 35
35 - SPI1
USART1 = 37
37 - USART1
USART2 = 38
38 - USART2
EXTI15_10 = 40
40 - EXTI15_10
RTC_ALARM = 41
41 - RTC_ALARM
DMA1_STREAM7 = 47
47 - DMA1_STREAM7
TIM5 = 50
50 - TIM5
TIM6_DAC = 54
54 - TIM6_DAC
DMA2_STREAM0 = 56
56 - DMA2_STREAM0
DMA2_STREAM1 = 57
57 - DMA2_STREAM1
DMA2_STREAM2 = 58
58 - DMA2_STREAM2
DMA2_STREAM3 = 59
59 - DMA2_STREAM3
DMA2_STREAM4 = 60
60 - DMA2_STREAM4
DMA2_STREAM5 = 68
68 - DMA2_STREAM5
DMA2_STREAM6 = 69
69 - DMA2_STREAM6
DMA2_STREAM7 = 70
70 - DMA2_STREAM7
RNG = 80
80 - RNG
FPU = 81
81 - FPU
FMPI2C1_EV = 95
95 - FMPI2C1_EV
FMPI2C1_ER = 96
96 - FMPI2C1_ER
LPTIM1 = 97
97 - LPTIM1
Trait Implementations§
§impl InterruptNumber for Interrupt
impl InterruptNumber for Interrupt
impl Copy for Interrupt
impl Eq for Interrupt
impl StructuralPartialEq for Interrupt
Auto Trait Implementations§
impl Freeze for Interrupt
impl RefUnwindSafe for Interrupt
impl Send for Interrupt
impl Sync for Interrupt
impl Unpin for Interrupt
impl UnwindSafe for Interrupt
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more
Source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
Source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
🔬This is a nightly-only experimental API. (
clone_to_uninit
)Source§impl<T> InterruptExt for Twhere
T: InterruptNumber + Copy,
impl<T> InterruptExt for Twhere
T: InterruptNumber + Copy,
Source§fn is_enabled(self) -> bool
fn is_enabled(self) -> bool
Check if interrupt is enabled.
Source§fn is_pending(self) -> bool
fn is_pending(self) -> bool
Check if interrupt is pending.
Source§fn get_priority(self) -> Priority
fn get_priority(self) -> Priority
Get the priority of the interrupt.
Source§fn set_priority(self, prio: Priority)
fn set_priority(self, prio: Priority)
Set the interrupt priority.
Source§fn set_priority_with_cs(self, _cs: CriticalSection<'_>, prio: Priority)
fn set_priority_with_cs(self, _cs: CriticalSection<'_>, prio: Priority)
Set the interrupt priority with an already-acquired critical section Read more