Struct ComplementaryPwm

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pub struct ComplementaryPwm<'d, T: AdvancedInstance4Channel> { /* private fields */ }

Expand description

PWM driver with support for standard and complementary outputs.

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impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T>

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pub fn new( tim: Peri<'d, T>, ch1: Option<PwmPin<'d, T, Ch1>>, ch1n: Option<ComplementaryPwmPin<'d, T, Ch1>>, ch2: Option<PwmPin<'d, T, Ch2>>, ch2n: Option<ComplementaryPwmPin<'d, T, Ch2>>, ch3: Option<PwmPin<'d, T, Ch3>>, ch3n: Option<ComplementaryPwmPin<'d, T, Ch3>>, ch4: Option<PwmPin<'d, T, Ch4>>, ch4n: Option<ComplementaryPwmPin<'d, T, Ch4>>, freq: Hertz, counting_mode: CountingMode, ) -> Self

Create a new complementary PWM driver.

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pub fn set_output_idle_state( &mut self, channels: &[Channel], polarity: IdlePolarity, )

Sets the idle output state for the given channels.

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pub fn set_off_state_selection_idle(&mut self, val: Ossi)

Set state of OSSI-bit in BDTR register

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pub fn get_off_state_selection_idle(&self) -> Ossi

Get state of OSSI-bit in BDTR register

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pub fn set_off_state_selection_run(&mut self, val: Ossr)

Set state of OSSR-bit in BDTR register

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pub fn get_off_state_selection_run(&self) -> Ossr

Get state of OSSR-bit in BDTR register

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pub fn trigger_software_break(&mut self, n: usize)

Trigger break input from software

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pub fn set_master_output_enable(&mut self, enable: bool)

Set Master Output Enable

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pub fn get_master_output_enable(&self) -> bool

Get Master Output Enable

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pub fn set_mms2(&mut self, mms2: Mms2)

Set Master Slave Mode 2

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pub fn set_repetition_counter(&mut self, val: u16)

Set Repetition Counter

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pub fn enable(&mut self, channel: Channel)

Enable the given channel.

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pub fn disable(&mut self, channel: Channel)

Disable the given channel.

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pub fn set_frequency(&mut self, freq: Hertz)

Set PWM frequency.

Note: when you call this, the max duty value changes, so you will have to call set_duty on all channels with the duty calculated based on the new max duty.

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pub fn get_max_duty(&self) -> u16

Get max duty value.

This value depends on the configured frequency and the timer’s clock rate from RCC.

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pub fn set_duty(&mut self, channel: Channel, duty: u16)

Set the duty for a given channel.

The value ranges from 0 for 0% duty, to get_max_duty for 100% duty, both included.

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pub fn set_polarity(&mut self, channel: Channel, polarity: OutputPolarity)

Set the output polarity for a given channel.

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pub fn set_main_polarity(&mut self, channel: Channel, polarity: OutputPolarity)

Set the main output polarity for a given channel.

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pub fn set_complementary_polarity( &mut self, channel: Channel, polarity: OutputPolarity, )

Set the complementary output polarity for a given channel.

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pub fn set_dead_time(&mut self, value: u16)

Set the dead time as a proportion of max_duty

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pub async fn waveform_up( &mut self, dma: Peri<'_, impl UpDma<T>>, channel: Channel, duty: &[u16], )

Generate a sequence of PWM waveform

Note: you will need to provide corresponding TIMx_UP DMA channel to use this method.

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pub async fn waveform_up_multi_channel( &mut self, dma: Peri<'_, impl UpDma<T>>, starting_channel: Channel, ending_channel: Channel, duty: &[u16], )

Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.

This method utilizes the timer’s DMA burst transfer capability to update multiple CCRx registers in sequence on each update event (UEV). The data is written via the DMAR register using the DMA base address (DBA) and burst length (DBL) configured in the DCR register.

The duty buffer must be structured as a flattened 2D array in row-major order, where each row represents a single update event and each column corresponds to a specific timer channel (starting from starting_channel up to and including ending_channel).

For example, if using channels 1 through 4, a buffer of 4 update steps might look like:

let dma_buf: [u16; 16] = [
    ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
    ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
    ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
    ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
];

Each group of N values (where N is number of channels) is transferred on one update event, updating the duty cycles of all selected channels simultaneously.

Note: You will need to provide corresponding TIMx_UP DMA channel to use this method. Also be aware that embassy timers use one of timers internally. It is possible to switch this timer by using time-driver-timX feature.

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