Embassy
embassy-stm32

Crates

git

Versions

stm32h742xg

Flavors

embassy_stm32::interrupt

Enum Interrupt

pub enum Interrupt {

Show 136 variants    WWDG = 0,
    PVD_AVD = 1,
    TAMP_STAMP = 2,
    RTC_WKUP = 3,
    FLASH = 4,
    RCC = 5,
    EXTI0 = 6,
    EXTI1 = 7,
    EXTI2 = 8,
    EXTI3 = 9,
    EXTI4 = 10,
    DMA1_STREAM0 = 11,
    DMA1_STREAM1 = 12,
    DMA1_STREAM2 = 13,
    DMA1_STREAM3 = 14,
    DMA1_STREAM4 = 15,
    DMA1_STREAM5 = 16,
    DMA1_STREAM6 = 17,
    ADC = 18,
    FDCAN1_IT0 = 19,
    FDCAN2_IT0 = 20,
    FDCAN1_IT1 = 21,
    FDCAN2_IT1 = 22,
    EXTI9_5 = 23,
    TIM1_BRK = 24,
    TIM1_UP = 25,
    TIM1_TRG_COM = 26,
    TIM1_CC = 27,
    TIM2 = 28,
    TIM3 = 29,
    TIM4 = 30,
    I2C1_EV = 31,
    I2C1_ER = 32,
    I2C2_EV = 33,
    I2C2_ER = 34,
    SPI1 = 35,
    SPI2 = 36,
    USART1 = 37,
    USART2 = 38,
    USART3 = 39,
    EXTI15_10 = 40,
    RTC_ALARM = 41,
    TIM8_BRK_TIM12 = 43,
    TIM8_UP_TIM13 = 44,
    TIM8_TRG_COM_TIM14 = 45,
    TIM8_CC = 46,
    DMA1_STREAM7 = 47,
    FMC = 48,
    SDMMC1 = 49,
    TIM5 = 50,
    SPI3 = 51,
    UART4 = 52,
    UART5 = 53,
    TIM6_DAC = 54,
    TIM7 = 55,
    DMA2_STREAM0 = 56,
    DMA2_STREAM1 = 57,
    DMA2_STREAM2 = 58,
    DMA2_STREAM3 = 59,
    DMA2_STREAM4 = 60,
    ETH = 61,
    ETH_WKUP = 62,
    FDCAN_CAL = 63,
    DMA2_STREAM5 = 68,
    DMA2_STREAM6 = 69,
    DMA2_STREAM7 = 70,
    USART6 = 71,
    I2C3_EV = 72,
    I2C3_ER = 73,
    OTG_HS_EP1_OUT = 74,
    OTG_HS_EP1_IN = 75,
    OTG_HS_WKUP = 76,
    OTG_HS = 77,
    DCMI = 78,
    RNG = 80,
    FPU = 81,
    UART7 = 82,
    UART8 = 83,
    SPI4 = 84,
    SPI5 = 85,
    SPI6 = 86,
    SAI1 = 87,
    DMA2D = 90,
    SAI2 = 91,
    QUADSPI = 92,
    LPTIM1 = 93,
    CEC = 94,
    I2C4_EV = 95,
    I2C4_ER = 96,
    SPDIF_RX = 97,
    OTG_FS_EP1_OUT = 98,
    OTG_FS_EP1_IN = 99,
    OTG_FS_WKUP = 100,
    OTG_FS = 101,
    DMAMUX1_OVR = 102,
    HRTIM1_MASTER = 103,
    HRTIM1_TIMA = 104,
    HRTIM1_TIMB = 105,
    HRTIM1_TIMC = 106,
    HRTIM1_TIMD = 107,
    HRTIM1_TIME = 108,
    HRTIM1_FLT = 109,
    DFSDM1_FLT0 = 110,
    DFSDM1_FLT1 = 111,
    DFSDM1_FLT2 = 112,
    DFSDM1_FLT3 = 113,
    SAI3 = 114,
    SWPMI1 = 115,
    TIM15 = 116,
    TIM16 = 117,
    TIM17 = 118,
    MDIOS_WKUP = 119,
    MDIOS = 120,
    MDMA = 122,
    SDMMC2 = 124,
    HSEM1 = 125,
    ADC3 = 127,
    DMAMUX2_OVR = 128,
    BDMA_CHANNEL0 = 129,
    BDMA_CHANNEL1 = 130,
    BDMA_CHANNEL2 = 131,
    BDMA_CHANNEL3 = 132,
    BDMA_CHANNEL4 = 133,
    BDMA_CHANNEL5 = 134,
    BDMA_CHANNEL6 = 135,
    BDMA_CHANNEL7 = 136,
    COMP = 137,
    LPTIM2 = 138,
    LPTIM3 = 139,
    LPTIM4 = 140,
    LPTIM5 = 141,
    LPUART1 = 142,
    CRS = 144,
    ECC = 145,
    SAI4 = 146,
    WAKEUP_PIN = 149,

}

Variants§

§

WWDG = 0

0 - WWDG

§

PVD_AVD = 1

1 - PVD_AVD

§

TAMP_STAMP = 2

2 - TAMP_STAMP

§

RTC_WKUP = 3

3 - RTC_WKUP

§

FLASH = 4

4 - FLASH

§

RCC = 5

5 - RCC

§

EXTI0 = 6

6 - EXTI0

§

EXTI1 = 7

7 - EXTI1

§

EXTI2 = 8

8 - EXTI2

§

EXTI3 = 9

9 - EXTI3

§

EXTI4 = 10

10 - EXTI4

§

DMA1_STREAM0 = 11

11 - DMA1_STREAM0

§

DMA1_STREAM1 = 12

12 - DMA1_STREAM1

§

DMA1_STREAM2 = 13

13 - DMA1_STREAM2

§

DMA1_STREAM3 = 14

14 - DMA1_STREAM3

§

DMA1_STREAM4 = 15

15 - DMA1_STREAM4

§

DMA1_STREAM5 = 16

16 - DMA1_STREAM5

§

DMA1_STREAM6 = 17

17 - DMA1_STREAM6

§

ADC = 18

18 - ADC

§

FDCAN1_IT0 = 19

19 - FDCAN1_IT0

§

FDCAN2_IT0 = 20

20 - FDCAN2_IT0

§

FDCAN1_IT1 = 21

21 - FDCAN1_IT1

§

FDCAN2_IT1 = 22

22 - FDCAN2_IT1

§

EXTI9_5 = 23

23 - EXTI9_5

§

TIM1_BRK = 24

24 - TIM1_BRK

§

TIM1_UP = 25

25 - TIM1_UP

§

TIM1_TRG_COM = 26

26 - TIM1_TRG_COM

§

TIM1_CC = 27

27 - TIM1_CC

§

TIM2 = 28

28 - TIM2

§

TIM3 = 29

29 - TIM3

§

TIM4 = 30

30 - TIM4

§

I2C1_EV = 31

31 - I2C1_EV

§

I2C1_ER = 32

32 - I2C1_ER

§

I2C2_EV = 33

33 - I2C2_EV

§

I2C2_ER = 34

34 - I2C2_ER

§

SPI1 = 35

35 - SPI1

§

SPI2 = 36

36 - SPI2

§

USART1 = 37

37 - USART1

§

USART2 = 38

38 - USART2

§

USART3 = 39

39 - USART3

§

EXTI15_10 = 40

40 - EXTI15_10

§

RTC_ALARM = 41

41 - RTC_ALARM

§

TIM8_BRK_TIM12 = 43

43 - TIM8_BRK_TIM12

§

TIM8_UP_TIM13 = 44

44 - TIM8_UP_TIM13

§

TIM8_TRG_COM_TIM14 = 45

45 - TIM8_TRG_COM_TIM14

§

TIM8_CC = 46

46 - TIM8_CC

§

DMA1_STREAM7 = 47

47 - DMA1_STREAM7

§

FMC = 48

48 - FMC

§

SDMMC1 = 49

49 - SDMMC1

§

TIM5 = 50

50 - TIM5

§

SPI3 = 51

51 - SPI3

§

UART4 = 52

52 - UART4

§

UART5 = 53

53 - UART5

§

TIM6_DAC = 54

54 - TIM6_DAC

§

TIM7 = 55

55 - TIM7

§

DMA2_STREAM0 = 56

56 - DMA2_STREAM0

§

DMA2_STREAM1 = 57

57 - DMA2_STREAM1

§

DMA2_STREAM2 = 58

58 - DMA2_STREAM2

§

DMA2_STREAM3 = 59

59 - DMA2_STREAM3

§

DMA2_STREAM4 = 60

60 - DMA2_STREAM4

§

ETH = 61

61 - ETH

§

ETH_WKUP = 62

62 - ETH_WKUP

§

FDCAN_CAL = 63

63 - FDCAN_CAL

§

DMA2_STREAM5 = 68

68 - DMA2_STREAM5

§

DMA2_STREAM6 = 69

69 - DMA2_STREAM6

§

DMA2_STREAM7 = 70

70 - DMA2_STREAM7

§

USART6 = 71

71 - USART6

§

I2C3_EV = 72

72 - I2C3_EV

§

I2C3_ER = 73

73 - I2C3_ER

§

OTG_HS_EP1_OUT = 74

74 - OTG_HS_EP1_OUT

§

OTG_HS_EP1_IN = 75

75 - OTG_HS_EP1_IN

§

OTG_HS_WKUP = 76

76 - OTG_HS_WKUP

§

OTG_HS = 77

77 - OTG_HS

§

DCMI = 78

78 - DCMI

§

RNG = 80

80 - RNG

§

FPU = 81

81 - FPU

§

UART7 = 82

82 - UART7

§

UART8 = 83

83 - UART8

§

SPI4 = 84

84 - SPI4

§

SPI5 = 85

85 - SPI5

§

SPI6 = 86

86 - SPI6

§

SAI1 = 87

87 - SAI1

§

DMA2D = 90

90 - DMA2D

§

SAI2 = 91

91 - SAI2

§

QUADSPI = 92

92 - QUADSPI

§

LPTIM1 = 93

93 - LPTIM1

§

CEC = 94

94 - CEC

§

I2C4_EV = 95

95 - I2C4_EV

§

I2C4_ER = 96

96 - I2C4_ER

§

SPDIF_RX = 97

97 - SPDIF_RX

§

OTG_FS_EP1_OUT = 98

98 - OTG_FS_EP1_OUT

§

OTG_FS_EP1_IN = 99

99 - OTG_FS_EP1_IN

§

OTG_FS_WKUP = 100

100 - OTG_FS_WKUP

§

OTG_FS = 101

101 - OTG_FS

§

DMAMUX1_OVR = 102

102 - DMAMUX1_OVR

§

HRTIM1_MASTER = 103

103 - HRTIM1_MASTER

§

HRTIM1_TIMA = 104

104 - HRTIM1_TIMA

§

HRTIM1_TIMB = 105

105 - HRTIM1_TIMB

§

HRTIM1_TIMC = 106

106 - HRTIM1_TIMC

§

HRTIM1_TIMD = 107

107 - HRTIM1_TIMD

§

HRTIM1_TIME = 108

108 - HRTIM1_TIME

§

HRTIM1_FLT = 109

109 - HRTIM1_FLT

§

DFSDM1_FLT0 = 110

110 - DFSDM1_FLT0

§

DFSDM1_FLT1 = 111

111 - DFSDM1_FLT1

§

DFSDM1_FLT2 = 112

112 - DFSDM1_FLT2

§

DFSDM1_FLT3 = 113

113 - DFSDM1_FLT3

§

SAI3 = 114

114 - SAI3

§

SWPMI1 = 115

115 - SWPMI1

§

TIM15 = 116

116 - TIM15

§

TIM16 = 117

117 - TIM16

§

TIM17 = 118

118 - TIM17

§

MDIOS_WKUP = 119

119 - MDIOS_WKUP

§

MDIOS = 120

120 - MDIOS

§

MDMA = 122

122 - MDMA

§

SDMMC2 = 124

124 - SDMMC2

§

HSEM1 = 125

125 - HSEM1

§

ADC3 = 127

127 - ADC3

§

DMAMUX2_OVR = 128

128 - DMAMUX2_OVR

§

BDMA_CHANNEL0 = 129

129 - BDMA_CHANNEL0

§

BDMA_CHANNEL1 = 130

130 - BDMA_CHANNEL1

§

BDMA_CHANNEL2 = 131

131 - BDMA_CHANNEL2

§

BDMA_CHANNEL3 = 132

132 - BDMA_CHANNEL3

§

BDMA_CHANNEL4 = 133

133 - BDMA_CHANNEL4

§

BDMA_CHANNEL5 = 134

134 - BDMA_CHANNEL5

§

BDMA_CHANNEL6 = 135

135 - BDMA_CHANNEL6

§

BDMA_CHANNEL7 = 136

136 - BDMA_CHANNEL7

§

COMP = 137

137 - COMP

§

LPTIM2 = 138

138 - LPTIM2

§

LPTIM3 = 139

139 - LPTIM3

§

LPTIM4 = 140

140 - LPTIM4

§

LPTIM5 = 141

141 - LPTIM5

§

LPUART1 = 142

142 - LPUART1

§

CRS = 144

144 - CRS

§

ECC = 145

145 - ECC

§

SAI4 = 146

146 - SAI4

§

WAKEUP_PIN = 149

149 - WAKEUP_PIN

Trait Implementations§

§

impl Clone for Interrupt

§

fn clone(&self) -> Interrupt

Returns a copy of the value. Read more
1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
§

impl Debug for Interrupt

§

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter. Read more
§

impl InterruptNumber for Interrupt

§

fn number(self) -> u16

Return the interrupt number associated with this variant. Read more
§

impl PartialEq for Interrupt

§

fn eq(&self, other: &Interrupt) -> bool

Tests for self and other values to be equal, and is used by ==.
1.0.0 · Source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
§

impl Copy for Interrupt

§

impl Eq for Interrupt

§

impl StructuralPartialEq for Interrupt

Auto Trait Implementations§

Blanket Implementations§

Source§

impl<T> Any for T
where T: 'static + ?Sized,

Source§

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
Source§

impl<T> Borrow<T> for T
where T: ?Sized,

Source§

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
Source§

impl<T> BorrowMut<T> for T
where T: ?Sized,

Source§

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
Source§

impl<T> CloneToUninit for T
where T: Clone,

Source§

unsafe fn clone_to_uninit(&self, dst: *mut T)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dst. Read more
Source§

impl<T> From<T> for T

Source§

fn from(t: T) -> T

Returns the argument unchanged.

Source§

impl<T> InterruptExt for T
where T: InterruptNumber + Copy,

Source§

unsafe fn enable(self)

Enable the interrupt.
Source§

fn disable(self)

Disable the interrupt.
Source§

fn is_active(self) -> bool

Check if interrupt is being handled.
Source§

fn is_enabled(self) -> bool

Check if interrupt is enabled.
Source§

fn is_pending(self) -> bool

Check if interrupt is pending.
Source§

fn pend(self)

Set interrupt pending.
Source§

fn unpend(self)

Unset interrupt pending.
Source§

fn get_priority(self) -> Priority

Get the priority of the interrupt.
Source§

fn set_priority(self, prio: Priority)

Set the interrupt priority.
Source§

fn set_priority_with_cs(self, _cs: CriticalSection<'_>, prio: Priority)

Set the interrupt priority with an already-acquired critical section Read more
Source§

impl<T, U> Into<U> for T
where U: From<T>,

Source§

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

Source§

impl<T, U> TryFrom<U> for T
where U: Into<T>,

Source§

type Error = Infallible

The type returned in the event of a conversion error.
Source§

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
Source§

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

Source§

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
Source§

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.