Struct SimplePwm

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pub struct SimplePwm<'d, T: GeneralInstance4Channel> { /* private fields */ }

Expand description

Simple PWM driver.

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impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T>

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pub fn new( tim: Peri<'d, T>, _ch1: Option<PwmPin<'d, T, Ch1>>, _ch2: Option<PwmPin<'d, T, Ch2>>, _ch3: Option<PwmPin<'d, T, Ch3>>, _ch4: Option<PwmPin<'d, T, Ch4>>, freq: Hertz, counting_mode: CountingMode, ) -> Self

Create a new simple PWM driver.

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pub fn channel(&mut self, channel: Channel) -> SimplePwmChannel<'_, T>

Get a single channel

If you need to use multiple channels, use Self::split.

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pub fn ch1(&mut self) -> SimplePwmChannel<'_, T>

Channel 1

This is just a convenience wrapper around Self::channel.

If you need to use multiple channels, use Self::split.

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pub fn ch2(&mut self) -> SimplePwmChannel<'_, T>

Channel 2

This is just a convenience wrapper around Self::channel.

If you need to use multiple channels, use Self::split.

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pub fn ch3(&mut self) -> SimplePwmChannel<'_, T>

Channel 3

This is just a convenience wrapper around Self::channel.

If you need to use multiple channels, use Self::split.

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pub fn ch4(&mut self) -> SimplePwmChannel<'_, T>

Channel 4

This is just a convenience wrapper around Self::channel.

If you need to use multiple channels, use Self::split.

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pub fn split(self) -> SimplePwmChannels<'static, T>
where 'd: 'static,

Splits a SimplePwm into four pwm channels.

This returns all four channels, including channels that aren’t configured with a PwmPin.

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pub fn set_frequency(&mut self, freq: Hertz)

Set PWM frequency.

Note: when you call this, the max duty value changes, so you will have to call set_duty on all channels with the duty calculated based on the new max duty.

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pub fn max_duty_cycle(&self) -> u16

Get max duty value.

This value depends on the configured frequency and the timer’s clock rate from RCC.

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pub async fn waveform_up( &mut self, dma: Peri<'_, impl UpDma<T>>, channel: Channel, duty: &[u16], )

Generate a sequence of PWM waveform

Note: you will need to provide corresponding TIMx_UP DMA channel to use this method.

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pub async fn waveform_up_multi_channel( &mut self, dma: Peri<'_, impl UpDma<T>>, starting_channel: Channel, ending_channel: Channel, duty: &[u16], )

Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.

This method utilizes the timer’s DMA burst transfer capability to update multiple CCRx registers in sequence on each update event (UEV). The data is written via the DMAR register using the DMA base address (DBA) and burst length (DBL) configured in the DCR register.

The duty buffer must be structured as a flattened 2D array in row-major order, where each row represents a single update event and each column corresponds to a specific timer channel (starting from starting_channel up to and including ending_channel).

For example, if using channels 1 through 4, a buffer of 4 update steps might look like:

let dma_buf: [u16; 16] = [ ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1 ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2 ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3 ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4 ];

Each group of N values (where N = number of channels) is transferred on one update event, updating the duty cycles of all selected channels simultaneously.

Note: you will need to provide corresponding TIMx_UP DMA channel to use this method.

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