Struct Sdmmc 

pub struct Sdmmc<'d> { /* private fields */ }

Sdmmc device

Implementations

impl<'d> Sdmmc<'d>

pub fn new_1bit<T: Instance>( sdmmc: Peri<'d, T>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + 'd, clk: Peri<'d, impl CkPin<T>>, cmd: Peri<'d, impl CmdPin<T>>, d0: Peri<'d, impl D0Pin<T>>, config: Config, ) -> Self

Create a new SDMMC driver, with 1 data lane.

pub fn new_4bit<T: Instance>( sdmmc: Peri<'d, T>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + 'd, clk: Peri<'d, impl CkPin<T>>, cmd: Peri<'d, impl CmdPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, config: Config, ) -> Self

Create a new SDMMC driver, with 4 data lanes.

impl<'d> Sdmmc<'d>

pub fn new_8bit<T: Instance>( sdmmc: Peri<'d, T>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + 'd, clk: Peri<'d, impl CkPin<T>>, cmd: Peri<'d, impl CmdPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, config: Config, ) -> Self

Create a new SDMMC driver, with 8 data lanes.

impl<'d> Sdmmc<'d>

pub fn new_1bit_with_vswitch<T: Instance>( sdmmc: Peri<'d, T>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + 'd, clk: Peri<'d, impl CkPin<T>>, cmd: Peri<'d, impl CmdPin<T>>, d0: Peri<'d, impl D0Pin<T>>, vswitch: Output<'d>, config: Config, ) -> Self

Create a new SDMMC driver, with 1 data lane and a UHS-I level- shifter select pin.

Only available on sdmmc_v3 (STM32N6) with feature = "time": other peripheral versions lack the required POWER/VSWITCH bits (v1) or are unvalidated (v2), and the switch handshake uses embassy_time::with_timeout to wait on hardware status flags.

The caller pre-constructs an Output for the board’s level- shifter select pin at its 3.3V level (polarity is per-board); the driver toggles it during the CMD11 handshake whenever the card accepts the S18A request on ACMD41.

pub fn new_4bit_with_vswitch<T: Instance>( sdmmc: Peri<'d, T>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + 'd, clk: Peri<'d, impl CkPin<T>>, cmd: Peri<'d, impl CmdPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, vswitch: Output<'d>, config: Config, ) -> Self

4 data lanes; see Self::new_1bit_with_vswitch.

pub fn new_1bit_with_vswitch_ckin<T: Instance>( sdmmc: Peri<'d, T>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + 'd, clk: Peri<'d, impl CkPin<T>>, cmd: Peri<'d, impl CmdPin<T>>, d0: Peri<'d, impl D0Pin<T>>, vswitch: Output<'d>, ckin: Peri<'d, impl CkinPin<T>>, config: Config, ) -> Self

1 data lane, plus UHS-I vswitch and a CKIN feedback-clock pin.

Only callable on SDMMC instances whose silicon exposes a CKIN signal — a CkinPin<T> trait impl must exist for the passed-in pin. With this constructor the driver is allowed to negotiate UHS-SDR50 (CMD6 function group 1 ID 2, CLKCR.SELCLKRX = 1); without it, acquire() caps at SDR25.

pub fn new_4bit_with_vswitch_ckin<T: Instance>( sdmmc: Peri<'d, T>, _irq: impl Binding<T::Interrupt, InterruptHandler<T>> + 'd, clk: Peri<'d, impl CkPin<T>>, cmd: Peri<'d, impl CmdPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, vswitch: Output<'d>, ckin: Peri<'d, impl CkinPin<T>>, config: Config, ) -> Self

4 data lanes; see Self::new_1bit_with_vswitch_ckin.

Trait Implementations

impl<'d> Drop for Sdmmc<'d>

fn drop(&mut self)

Executes the destructor for this type.