Struct Xspi 

pub struct Xspi<'d, T: Instance, M: PeriMode> { /* private fields */ }

XSPI driver.

Implementations

impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M>

pub fn enable_memory_mapped_mode( &mut self, read_config: TransferConfig, write_config: TransferConfig, ) -> Result<(), XspiError>

Enter memory mode. The Input read_config is used to configure the read operation in memory mode

pub fn disable_memory_mapped_mode(&mut self)

Quit from memory mapped mode

pub fn set_clock_prescaler(&mut self, prescaler: u8)

Set clock prescaler dynamically after initialization.

• 0 = bypass (maximum speed, XSPI clock = kernel clock)
• 1-255 = divide by (N+1)

This can be called after init to change clock speed, matching ST HAL’s HAL_XSPI_SetClockPrescaler() behavior.

pub fn blocking_command( &mut self, command: &TransferConfig, ) -> Result<(), XspiError>

Function used to control or configure the target device without data transfer

pub fn blocking_read<W: Word>( &mut self, buf: &mut [W], transaction: TransferConfig, ) -> Result<(), XspiError>

Blocking read with byte by byte data transfer

pub fn blocking_write<W: Word>( &mut self, buf: &[W], transaction: TransferConfig, ) -> Result<(), XspiError>

Blocking write with byte by byte data transfer

pub fn set_config(&mut self, config: &Config)

Set new bus configuration

pub fn get_config(&self) -> Config

Get current configuration

impl<'d, T: Instance> Xspi<'d, T, Blocking>

pub fn new_blocking_singlespi( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, config: Config, ) -> Self

Create new blocking XSPI driver for a single spi external chip

pub fn new_blocking_dualspi( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, config: Config, ) -> Self

Create new blocking XSPI driver for a dualspi external chip

pub fn new_blocking_quadspi( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, config: Config, ) -> Self

Create new blocking XSPI driver for a quadspi external chip

pub fn new_blocking_dualquadspi( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, config: Config, ) -> Self

Create new blocking XSPI driver for two quadspi external chips

pub fn new_blocking_xspi( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, config: Config, ) -> Self

Create new blocking XSPI driver for xspi external chips

pub fn new_blocking_xspi_dqs( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, dqs0: Peri<'d, impl DQS0Pin<T>>, config: Config, ) -> Self

Create new blocking XSPI driver for octo-spi with DQS pin support. Required for high-speed DTR mode operation (>145 MHz).

pub fn new_blocking_xspi_hexa( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, d8: Peri<'d, impl D8Pin<T>>, d9: Peri<'d, impl D9Pin<T>>, d10: Peri<'d, impl D10Pin<T>>, d11: Peri<'d, impl D11Pin<T>>, d12: Peri<'d, impl D12Pin<T>>, d13: Peri<'d, impl D13Pin<T>>, d14: Peri<'d, impl D14Pin<T>>, d15: Peri<'d, impl D15Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, config: Config, ) -> Self

Create new blocking XSPI driver for 16-bit hexadeca-spi external chips

pub fn new_blocking_xspi_hexa_dqs( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, d8: Peri<'d, impl D8Pin<T>>, d9: Peri<'d, impl D9Pin<T>>, d10: Peri<'d, impl D10Pin<T>>, d11: Peri<'d, impl D11Pin<T>>, d12: Peri<'d, impl D12Pin<T>>, d13: Peri<'d, impl D13Pin<T>>, d14: Peri<'d, impl D14Pin<T>>, d15: Peri<'d, impl D15Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, dqs0: Peri<'d, impl DQS0Pin<T>>, config: Config, ) -> Self

Create new blocking XSPI driver for a Hexadeca-SPI external chip with DQS pin Required for Xccela protocol devices (like APS256XXN PSRAM) that use DTR mode

pub fn new_blocking_xspi_hexa_dqs_dual( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, d8: Peri<'d, impl D8Pin<T>>, d9: Peri<'d, impl D9Pin<T>>, d10: Peri<'d, impl D10Pin<T>>, d11: Peri<'d, impl D11Pin<T>>, d12: Peri<'d, impl D12Pin<T>>, d13: Peri<'d, impl D13Pin<T>>, d14: Peri<'d, impl D14Pin<T>>, d15: Peri<'d, impl D15Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, dqs0: Peri<'d, impl DQS0Pin<T>>, dqs1: Peri<'d, impl DQS1Pin<T>>, config: Config, ) -> Self

Create new blocking XSPI driver for Hexadeca-SPI with dual DQS pins Required for APS256XX PSRAM on STM32N6570-DK which uses both DQS0 and DQS1

impl<'d, T: Instance> Xspi<'d, T, Async>

pub fn new_singlespi<D: XDma<T>>( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, dma: Peri<'d, D>, _irq: impl Binding<D::Interrupt, InterruptHandler<D>> + 'd, config: Config, ) -> Self

Create new async XSPI driver for a single spi external chip

pub fn new_dualspi<D: XDma<T>>( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, dma: Peri<'d, D>, _irq: impl Binding<D::Interrupt, InterruptHandler<D>> + 'd, config: Config, ) -> Self

Create new async XSPI driver for a dualspi external chip

pub fn new_quadspi<D: XDma<T>>( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, dma: Peri<'d, D>, _irq: impl Binding<D::Interrupt, InterruptHandler<D>> + 'd, config: Config, ) -> Self

Create new async XSPI driver for a quadspi external chip

pub fn new_dualquadspi<D: XDma<T>>( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, dma: Peri<'d, D>, _irq: impl Binding<D::Interrupt, InterruptHandler<D>> + 'd, config: Config, ) -> Self

Create new async XSPI driver for two quadspi external chips

pub fn new_xspi<D: XDma<T>>( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, dma: Peri<'d, D>, _irq: impl Binding<D::Interrupt, InterruptHandler<D>> + 'd, config: Config, ) -> Self

Create new async XSPI driver for xspi external chips

pub fn new_xspi_dqs<D: XDma<T>>( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, dqs0: Peri<'d, impl DQS0Pin<T>>, dma: Peri<'d, D>, _irq: impl Binding<D::Interrupt, InterruptHandler<D>> + 'd, config: Config, ) -> Self

Create new async XSPI driver for octo-spi with DQS pin support. Required for high-speed DTR mode operation (>145 MHz).

pub fn new_xspi_hexa<D: XDma<T>>( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, d8: Peri<'d, impl D8Pin<T>>, d9: Peri<'d, impl D9Pin<T>>, d10: Peri<'d, impl D10Pin<T>>, d11: Peri<'d, impl D11Pin<T>>, d12: Peri<'d, impl D12Pin<T>>, d13: Peri<'d, impl D13Pin<T>>, d14: Peri<'d, impl D14Pin<T>>, d15: Peri<'d, impl D15Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, dma: Peri<'d, D>, _irq: impl Binding<D::Interrupt, InterruptHandler<D>> + 'd, config: Config, ) -> Self

Create new async XSPI driver for 16-bit hexadeca-spi external chips

pub fn new_xspi_hexa_dqs<D: XDma<T>>( peri: Peri<'d, T>, clk: Peri<'d, impl CLKPin<T>>, d0: Peri<'d, impl D0Pin<T>>, d1: Peri<'d, impl D1Pin<T>>, d2: Peri<'d, impl D2Pin<T>>, d3: Peri<'d, impl D3Pin<T>>, d4: Peri<'d, impl D4Pin<T>>, d5: Peri<'d, impl D5Pin<T>>, d6: Peri<'d, impl D6Pin<T>>, d7: Peri<'d, impl D7Pin<T>>, d8: Peri<'d, impl D8Pin<T>>, d9: Peri<'d, impl D9Pin<T>>, d10: Peri<'d, impl D10Pin<T>>, d11: Peri<'d, impl D11Pin<T>>, d12: Peri<'d, impl D12Pin<T>>, d13: Peri<'d, impl D13Pin<T>>, d14: Peri<'d, impl D14Pin<T>>, d15: Peri<'d, impl D15Pin<T>>, ncs: Peri<'d, impl NCSEither<T>>, dqs0: Peri<'d, impl DQS0Pin<T>>, dma: Peri<'d, D>, _irq: impl Binding<D::Interrupt, InterruptHandler<D>> + 'd, config: Config, ) -> Self

Create new async XSPI driver for hexadeca-spi with DQS pin support. Required for high-speed DTR mode operation (>145 MHz).

pub fn blocking_read_dma<W: Word>( &mut self, buf: &mut [W], transaction: TransferConfig, ) -> Result<(), XspiError>

Blocking read with DMA transfer

pub fn blocking_write_dma<W: Word>( &mut self, buf: &[W], transaction: TransferConfig, ) -> Result<(), XspiError>

Blocking write with DMA transfer

pub async fn read<W: Word>( &mut self, buf: &mut [W], transaction: TransferConfig, ) -> Result<(), XspiError>

Asynchronous read from external device

pub async fn write<W: Word>( &mut self, buf: &[W], transaction: TransferConfig, ) -> Result<(), XspiError>

Asynchronous write to external device

Trait Implementations

impl<'d, T: Instance, M: PeriMode> Drop for Xspi<'d, T, M>

fn drop(&mut self)

Executes the destructor for this type.

impl<'d, T: Instance, M: PeriMode> GetConfig for Xspi<'d, T, M>

type Config = Config

The configuration type used by this driver.

fn get_config(&self) -> Self::Config

Get the configuration of the driver.

impl<'d, T: Instance, M: PeriMode> SetConfig for Xspi<'d, T, M>

type Config = Config

The configuration type used by this driver.

type ConfigError = ()

The error type that can occur if set_config fails.

fn set_config(&mut self, config: &Self::Config) -> Result<(), ()>

Set the configuration of the driver.