Struct Timer 

pub struct Timer<'d, T: CoreInstance> { /* private fields */ }

Low-level timer driver.

Implementations

impl<'d, T: CoreInstance> Timer<'d, T>

pub fn new(tim: Peri<'d, T>) -> Self

Create a new timer driver.

pub fn regs_core(&self) -> TimCore

Get access to the virutal core 16bit timer registers.

Note: This works even if the timer is more capable, because registers for the less capable timers are a subset. This allows writing a driver for a given set of capabilities, and having it transparently work with more capable timers.

pub fn start(&self)

Start the timer.

pub fn stop(&self)

Stop the timer.

pub fn reset(&self)

Reset the counter value to 0

pub fn bits(&self) -> TimerBits

get the capability of the timer

pub fn set_frequency(&self, frequency: Hertz)

Set the frequency of how many times per second the timer counts up to the max value or down to 0.

This means that in the default edge-aligned mode, the timer counter will wrap around at the same frequency as is being set. In center-aligned mode (which not all timers support), the wrap-around frequency is effectively halved because it needs to count up and down.

pub fn set_tick_freq(&mut self, freq: Hertz)

Set tick frequency.

pub fn clear_update_interrupt(&self) -> bool

Clear update interrupt.

Returns whether the update interrupt flag was set.

pub fn enable_update_interrupt(&self, enable: bool)

Enable/disable the update interrupt.

pub fn set_autoreload_preload(&self, enable: bool)

Enable/disable autoreload preload.

pub fn get_frequency(&self) -> Hertz

Get the timer frequency.

pub fn get_clock_frequency(&self) -> Hertz

Get the clock frequency of the timer (before prescaler is applied).

impl<'d, T: BasicNoCr2Instance> Timer<'d, T>

pub fn regs_basic_no_cr2(&self) -> TimBasicNoCr2

Get access to the Baisc 16bit timer registers.

Note: This works even if the timer is more capable, because registers for the less capable timers are a subset. This allows writing a driver for a given set of capabilities, and having it transparently work with more capable timers.

pub fn enable_update_dma(&self, enable: bool)

Enable/disable the update dma.

pub fn get_update_dma_state(&self) -> bool

Get the update dma enable/disable state.

impl<'d, T: BasicInstance> Timer<'d, T>

pub fn regs_basic(&self) -> TimBasic

Get access to the Baisc 16bit timer registers.

Note: This works even if the timer is more capable, because registers for the less capable timers are a subset. This allows writing a driver for a given set of capabilities, and having it transparently work with more capable timers.

impl<'d, T: GeneralInstance1Channel> Timer<'d, T>

pub fn regs_1ch(&self) -> Tim1ch

Get access to the general purpose 1 channel 16bit timer registers.

Note: This works even if the timer is more capable, because registers for the less capable timers are a subset. This allows writing a driver for a given set of capabilities, and having it transparently work with more capable timers.

pub fn set_clock_division(&self, ckd: Ckd)

Set clock divider.

pub fn get_max_compare_value(&self) -> u32

Get max compare value. This depends on the timer frequency and the clock frequency from RCC.

pub fn set_max_compare_value(&self, ticks: u32)

Set the max compare value.

An update event is generated to load the new value. The update event is generated such that it will not cause an interrupt or DMA request.

impl<'d, T: GeneralInstance2Channel> Timer<'d, T>

pub fn regs_2ch(&self) -> Tim2ch

Get access to the general purpose 2 channel 16bit timer registers.

Note: This works even if the timer is more capable, because registers for the less capable timers are a subset. This allows writing a driver for a given set of capabilities, and having it transparently work with more capable timers.

impl<'d, T: GeneralInstance4Channel> Timer<'d, T>

pub fn regs_gp16(&self) -> TimGp16

Get access to the general purpose 16bit timer registers.

Note: This works even if the timer is more capable, because registers for the less capable timers are a subset. This allows writing a driver for a given set of capabilities, and having it transparently work with more capable timers.

pub fn enable_outputs(&self)

Enable timer outputs.

pub fn set_counting_mode(&self, mode: CountingMode)

Set counting mode.

pub fn get_counting_mode(&self) -> CountingMode

Get counting mode.

pub fn set_input_capture_filter(&self, channel: Channel, icf: FilterValue)

Set input capture filter.

pub fn clear_input_interrupt(&self, channel: Channel)

Clear input interrupt.

pub fn get_input_interrupt(&self, channel: Channel) -> bool

Get input interrupt.

pub fn enable_input_interrupt(&self, channel: Channel, enable: bool)

Enable input interrupt.

pub fn set_input_capture_prescaler(&self, channel: Channel, factor: u8)

Set input capture prescaler.

pub fn set_input_ti_selection(&self, channel: Channel, tisel: InputTISelection)

Set input TI selection.

pub fn set_input_capture_mode(&self, channel: Channel, mode: InputCaptureMode)

Set input capture mode.

pub fn set_output_compare_mode(&self, channel: Channel, mode: OutputCompareMode)

Set output compare mode.

pub fn set_output_polarity(&self, channel: Channel, polarity: OutputPolarity)

Set output polarity.

pub fn enable_channel(&self, channel: Channel, enable: bool)

Enable/disable a channel.

pub fn get_channel_enable_state(&self, channel: Channel) -> bool

Get enable/disable state of a channel

pub fn set_compare_value(&self, channel: Channel, value: u32)

Set compare value for a channel.

pub fn get_compare_value(&self, channel: Channel) -> u32

Get compare value for a channel.

pub async fn waveform_up( &mut self, dma: Peri<'_, impl UpDma<T>>, channel: Channel, duty: &[u16], )

Generate a sequence of PWM waveform

Note: you will need to provide corresponding TIMx_UP DMA channel to use this method.

pub async fn waveform_up_multi_channel( &mut self, dma: Peri<'_, impl UpDma<T>>, starting_channel: Channel, ending_channel: Channel, duty: &[u16], )

Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.

This method utilizes the timer’s DMA burst transfer capability to update multiple CCRx registers in sequence on each update event (UEV). The data is written via the DMAR register using the DMA base address (DBA) and burst length (DBL) configured in the DCR register.

The duty buffer must be structured as a flattened 2D array in row-major order, where each row represents a single update event and each column corresponds to a specific timer channel (starting from starting_channel up to and including ending_channel).

For example, if using channels 1 through 4, a buffer of 4 update steps might look like:

let dma_buf: [u16; 16] = [
    ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
    ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
    ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
    ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
];

Each group of N values (where N is number of channels) is transferred on one update event, updating the duty cycles of all selected channels simultaneously.

Note: You will need to provide corresponding TIMx_UP DMA channel to use this method. Also be aware that embassy timers use one of timers internally. It is possible to switch this timer by using time-driver-timX feature.

pub async fn waveform<C: TimerChannel>( &mut self, dma: Peri<'_, impl Dma<T, C>>, duty: &[u16], )

Generate a sequence of PWM waveform

pub fn get_capture_value(&self, channel: Channel) -> u32

Get capture value for a channel.

pub fn set_output_compare_preload(&self, channel: Channel, preload: bool)

Set output compare preload.

pub fn get_cc_dma_selection(&self) -> Ccds

Get capture compare DMA selection

pub fn set_cc_dma_selection(&self, ccds: Ccds)

Set capture compare DMA selection

pub fn get_cc_dma_enable_state(&self, channel: Channel) -> bool

Get capture compare DMA enable state

pub fn set_cc_dma_enable_state(&self, channel: Channel, ccde: bool)

Set capture compare DMA enable state

pub fn set_master_mode(&self, mms: MasterMode)

Set Timer Master Mode

pub fn set_slave_mode(&self, sms: SlaveMode)

Set Timer Slave Mode

pub fn set_trigger_source(&self, ts: TriggerSource)

Set Timer Trigger Source

impl<'d, T: GeneralInstance32bit4Channel> Timer<'d, T>

pub fn regs_gp32(&self) -> TimGp32

Get access to the general purpose 32bit timer registers.

Note: This works even if the timer is more capable, because registers for the less capable timers are a subset. This allows writing a driver for a given set of capabilities, and having it transparently work with more capable timers.

impl<'d, T: AdvancedInstance1Channel> Timer<'d, T>

pub fn regs_1ch_cmp(&self) -> Tim1chCmp

Get access to the general purpose 1 channel with one complementary 16bit timer registers.

Note: This works even if the timer is more capable, because registers for the less capable timers are a subset. This allows writing a driver for a given set of capabilities, and having it transparently work with more capable timers.

pub fn set_dead_time_clock_division(&self, value: Ckd)

Set clock divider for the dead time.

pub fn set_dead_time_value(&self, value: u8)

Set dead time, as a fraction of the max duty value.

pub fn set_ossi(&self, val: Ossi)

Set state of OSSI-bit in BDTR register

pub fn get_ossi(&self) -> Ossi

Get state of OSSI-bit in BDTR register

pub fn set_ossr(&self, val: Ossr)

Set state of OSSR-bit in BDTR register

pub fn get_ossr(&self) -> Ossr

Get state of OSSR-bit in BDTR register

pub fn set_moe(&self, enable: bool)

Set state of MOE-bit in BDTR register to en-/disable output

pub fn get_moe(&self) -> bool

Get state of MOE-bit in BDTR register

impl<'d, T: AdvancedInstance2Channel> Timer<'d, T>

pub fn regs_2ch_cmp(&self) -> Tim2chCmp

Get access to the general purpose 2 channel with one complementary 16bit timer registers.

Note: This works even if the timer is more capable, because registers for the less capable timers are a subset. This allows writing a driver for a given set of capabilities, and having it transparently work with more capable timers.

impl<'d, T: AdvancedInstance4Channel> Timer<'d, T>

pub fn regs_advanced(&self) -> TimAdv

Get access to the advanced timer registers.

pub fn set_complementary_output_polarity( &self, channel: Channel, polarity: OutputPolarity, )

Set complementary output polarity.

pub fn enable_complementary_channel(&self, channel: Channel, enable: bool)

Enable/disable a complementary channel.

pub fn set_ois(&self, channel: Channel, val: bool)

Set Output Idle State

pub fn set_oisn(&self, channel: Channel, val: bool)

Set Output Idle State Complementary Channel

pub fn set_mms2_selection(&self, mms2: Mms2)

Set master mode selection 2

pub fn set_repetition_counter(&self, val: u16)

Set repetition counter

pub fn trigger_software_break(&self, n: usize)

Trigger software break 1 or 2 Setting this bit generates a break event. This bit is automatically cleared by the hardware.

Trait Implementations

impl<'d, T: CoreInstance> Drop for Timer<'d, T>

fn drop(&mut self)

Executes the destructor for this type.