Struct Pll

pub struct Pll {
    pub source: PllSource,
    pub prediv: PllPreDiv,
    pub mul: PllMul,
    pub divp: Option<PllDiv>,
    pub divq: Option<PllDiv>,
    pub divr: Option<PllDiv>,
}

Fields

source: PllSource

The clock source for the PLL.

prediv: PllPreDiv

The PLL pre-divider.

The clock speed of the source divided by m must be between 4 and 16 MHz.

mul: PllMul

The PLL multiplier.

The multiplied clock – source divided by m times n – must be between 128 and 544 MHz. The upper limit may be lower depending on the Config { voltage_range }.

divp: Option<PllDiv>

The divider for the P output.

The P output is one of several options that can be used to feed the SAI/MDF/ADF Clock mux’s.

divq: Option<PllDiv>

The divider for the Q output.

The Q ouput is one of severals options that can be used to feed the 48MHz clocks and the OCTOSPI clock. It may also be used on the MDF/ADF clock mux’s.

divr: Option<PllDiv>

The divider for the R output.

When used to drive the system clock, source divided by m times n divided by r must not exceed 160 MHz. System clocks above 55 MHz require a non-default Config { voltage_range }.

Trait Implementations

impl Clone for Pll

fn clone(&self) -> Pll

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Pll