Enum OutputCompareMode 

pub enum OutputCompareMode {
    Frozen,
    ActiveOnMatch,
    InactiveOnMatch,
    Toggle,
    ForceInactive,
    ForceActive,
    PwmMode1,
    PwmMode2,
    OnePulseMode1,
    OnePulseMode2,
    CombinedPwmMode1,
    CombinedPwmMode2,
    AsymmetricPwmMode1,
    AsymmetricPwmMode2,
}

Output compare mode.

Variants

Frozen

The comparison between the output compare register TIMx_CCRx and the counter TIMx_CNT has no effect on the outputs. (this mode is used to generate a timing base).

ActiveOnMatch

Set channel to active level on match. OCxREF signal is forced high when the counter TIMx_CNT matches the capture/compare register x (TIMx_CCRx).

InactiveOnMatch

Set channel to inactive level on match. OCxREF signal is forced low when the counter TIMx_CNT matches the capture/compare register x (TIMx_CCRx).

Toggle

Toggle - OCxREF toggles when TIMx_CNT=TIMx_CCRx.

ForceInactive

Force inactive level - OCxREF is forced low.

ForceActive

Force active level - OCxREF is forced high.

PwmMode1

PWM mode 1 - In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRx else inactive. In downcounting, channel is inactive (OCxREF=0) as long as TIMx_CNT>TIMx_CCRx else active (OCxREF=1).

PwmMode2

PWM mode 2 - In upcounting, channel is inactive as long as TIMx_CNT<TIMx_CCRx else active. In downcounting, channel is active as long as TIMx_CNT>TIMx_CCRx else inactive.

OnePulseMode1

In up-counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.

OnePulseMode2

In up-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.

CombinedPwmMode1

Combined PWM mode 1 - tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.

CombinedPwmMode2

Combined PWM mode 2 - tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.

AsymmetricPwmMode1

tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is counting down.

AsymmetricPwmMode2

tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is counting down.

Trait Implementations

impl Clone for OutputCompareMode

fn clone(&self) -> OutputCompareMode

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl From<OutputCompareMode> for Ocm

fn from(mode: OutputCompareMode) -> Self

Converts to this type from the input type.

impl Copy for OutputCompareMode