#[repr(transparent)]pub struct Csw(pub u32);Expand description
CRC mode register
Tuple Fields§
§0: u32Implementations§
Source§impl Csw
impl Csw
Sourcepub const fn resynch_req(&self) -> bool
pub const fn resynch_req(&self) -> bool
Debugger will set this bit to 1 to request a resynchronrisation
Sourcepub const fn set_resynch_req(&mut self, val: bool)
pub const fn set_resynch_req(&mut self, val: bool)
Debugger will set this bit to 1 to request a resynchronrisation
Sourcepub const fn req_pending(&self) -> bool
pub const fn req_pending(&self) -> bool
Request is pending from debugger (i.e unread value in REQUEST)
Sourcepub const fn set_req_pending(&mut self, val: bool)
pub const fn set_req_pending(&mut self, val: bool)
Request is pending from debugger (i.e unread value in REQUEST)
Sourcepub const fn dbg_or_err(&self) -> bool
pub const fn dbg_or_err(&self) -> bool
Debugger overrun error (previous REQUEST overwritten before being picked up by ROM)
Sourcepub const fn set_dbg_or_err(&mut self, val: bool)
pub const fn set_dbg_or_err(&mut self, val: bool)
Debugger overrun error (previous REQUEST overwritten before being picked up by ROM)
Sourcepub const fn ahb_or_err(&self) -> bool
pub const fn ahb_or_err(&self) -> bool
AHB overrun Error (Return value overwritten by ROM)
Sourcepub const fn set_ahb_or_err(&mut self, val: bool)
pub const fn set_ahb_or_err(&mut self, val: bool)
AHB overrun Error (Return value overwritten by ROM)
Sourcepub const fn soft_reset(&self) -> bool
pub const fn soft_reset(&self) -> bool
Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to this bit will cause a soft reset for DM.
Sourcepub const fn set_soft_reset(&mut self, val: bool)
pub const fn set_soft_reset(&mut self, val: bool)
Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to this bit will cause a soft reset for DM.
Sourcepub const fn chip_reset_req(&self) -> bool
pub const fn chip_reset_req(&self) -> bool
Write only bit. Once written will cause the chip to reset (note that the DM is not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event)
Sourcepub const fn set_chip_reset_req(&mut self, val: bool)
pub const fn set_chip_reset_req(&mut self, val: bool)
Write only bit. Once written will cause the chip to reset (note that the DM is not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event)