#[repr(transparent)]pub struct Cfg(pub u32);Expand description
Configuration register for DMA channel .
Tuple Fields§
§0: u32Implementations§
Source§impl Cfg
impl Cfg
Sourcepub const fn periphreqen(&self) -> bool
pub const fn periphreqen(&self) -> bool
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
Sourcepub const fn set_periphreqen(&mut self, val: bool)
pub const fn set_periphreqen(&mut self, val: bool)
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
Sourcepub const fn set_hwtrigen(&mut self, val: bool)
pub const fn set_hwtrigen(&mut self, val: bool)
Hardware Triggering Enable for this channel.
Sourcepub const fn trigpol(&self) -> Trigpol
pub const fn trigpol(&self) -> Trigpol
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
Sourcepub const fn set_trigpol(&mut self, val: Trigpol)
pub const fn set_trigpol(&mut self, val: Trigpol)
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
Sourcepub const fn trigtype(&self) -> Trigtype
pub const fn trigtype(&self) -> Trigtype
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
Sourcepub const fn set_trigtype(&mut self, val: Trigtype)
pub const fn set_trigtype(&mut self, val: Trigtype)
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
Sourcepub const fn trigburst(&self) -> Trigburst
pub const fn trigburst(&self) -> Trigburst
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
Sourcepub const fn set_trigburst(&mut self, val: Trigburst)
pub const fn set_trigburst(&mut self, val: Trigburst)
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
Sourcepub const fn burstpower(&self) -> u8
pub const fn burstpower(&self) -> u8
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
Sourcepub const fn set_burstpower(&mut self, val: u8)
pub const fn set_burstpower(&mut self, val: u8)
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
Sourcepub const fn srcburstwrap(&self) -> bool
pub const fn srcburstwrap(&self) -> bool
Source Burst Wrap. When enabled, the source data address for the DMA is ‘wrapped’, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
Sourcepub const fn set_srcburstwrap(&mut self, val: bool)
pub const fn set_srcburstwrap(&mut self, val: bool)
Source Burst Wrap. When enabled, the source data address for the DMA is ‘wrapped’, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
Sourcepub const fn dstburstwrap(&self) -> bool
pub const fn dstburstwrap(&self) -> bool
Destination Burst Wrap. When enabled, the destination data address for the DMA is ‘wrapped’, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
Sourcepub const fn set_dstburstwrap(&mut self, val: bool)
pub const fn set_dstburstwrap(&mut self, val: bool)
Destination Burst Wrap. When enabled, the destination data address for the DMA is ‘wrapped’, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
Sourcepub const fn chpriority(&self) -> u8
pub const fn chpriority(&self) -> u8
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
Sourcepub const fn set_chpriority(&mut self, val: u8)
pub const fn set_chpriority(&mut self, val: u8)
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority.