#[repr(transparent)]pub struct Scr(pub u32);Expand description
The SCR controls features of entry to and exit from low-power state.
Tuple Fields§
§0: u32Implementations§
Source§impl Scr
impl Scr
Sourcepub const fn sleeponexit(&self) -> bool
pub const fn sleeponexit(&self) -> bool
Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states.
Sourcepub const fn set_sleeponexit(&mut self, val: bool)
pub const fn set_sleeponexit(&mut self, val: bool)
Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states.
Sourcepub const fn sleepdeep(&self) -> Sleepdeep
pub const fn sleepdeep(&self) -> Sleepdeep
Controls whether the processor uses sleep or deep sleep as its low-power mode. This bit is not banked between Security states.
Sourcepub const fn set_sleepdeep(&mut self, val: Sleepdeep)
pub const fn set_sleepdeep(&mut self, val: Sleepdeep)
Controls whether the processor uses sleep or deep sleep as its low-power mode. This bit is not banked between Security states.
Sourcepub const fn sleepdeeps(&self) -> Sleepdeeps
pub const fn sleepdeeps(&self) -> Sleepdeeps
Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states.
Sourcepub const fn set_sleepdeeps(&mut self, val: Sleepdeeps)
pub const fn set_sleepdeeps(&mut self, val: Sleepdeeps)
Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states.
Sourcepub const fn sevonpend(&self) -> Sevonpend
pub const fn sevonpend(&self) -> Sevonpend
Send Event on Pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states.
Sourcepub const fn set_sevonpend(&mut self, val: Sevonpend)
pub const fn set_sevonpend(&mut self, val: Sevonpend)
Send Event on Pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states.