#[repr(transparent)]pub struct Config(pub u32);Expand description
SCT configuration register
Tuple Fields§
§0: u32Implementations§
Source§impl Config
impl Config
Sourcepub const fn set_clkmode(&mut self, val: Clkmode)
pub const fn set_clkmode(&mut self, val: Clkmode)
SCT clock mode
Sourcepub const fn cksel(&self) -> Cksel
pub const fn cksel(&self) -> Cksel
SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register.
Sourcepub const fn set_cksel(&mut self, val: Cksel)
pub const fn set_cksel(&mut self, val: Cksel)
SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register.
Sourcepub const fn noreload_l(&self) -> bool
pub const fn noreload_l(&self) -> bool
A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
Sourcepub const fn set_noreload_l(&mut self, val: bool)
pub const fn set_noreload_l(&mut self, val: bool)
A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
Sourcepub const fn noreload_h(&self) -> bool
pub const fn noreload_h(&self) -> bool
A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
Sourcepub const fn set_noreload_h(&mut self, val: bool)
pub const fn set_noreload_h(&mut self, val: bool)
A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
Sourcepub const fn insync(&self) -> u8
pub const fn insync(&self) -> u8
Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field.
Sourcepub const fn set_insync(&mut self, val: u8)
pub const fn set_insync(&mut self, val: u8)
Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field.
Sourcepub const fn autolimit_l(&self) -> bool
pub const fn autolimit_l(&self) -> bool
A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
Sourcepub const fn set_autolimit_l(&mut self, val: bool)
pub const fn set_autolimit_l(&mut self, val: bool)
A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
Sourcepub const fn autolimit_h(&self) -> bool
pub const fn autolimit_h(&self) -> bool
A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
Sourcepub const fn set_autolimit_h(&mut self, val: bool)
pub const fn set_autolimit_h(&mut self, val: bool)
A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.