#[repr(transparent)]pub struct Ctrl(pub u32);Expand description
SCT control register
Tuple Fields§
§0: u32Implementations§
Source§impl Ctrl
impl Ctrl
Sourcepub const fn down_l(&self) -> bool
pub const fn down_l(&self) -> bool
This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
Sourcepub const fn set_down_l(&mut self, val: bool)
pub const fn set_down_l(&mut self, val: bool)
This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
Sourcepub const fn stop_l(&self) -> bool
pub const fn stop_l(&self) -> bool
When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes.
Sourcepub const fn set_stop_l(&mut self, val: bool)
pub const fn set_stop_l(&mut self, val: bool)
When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes.
Sourcepub const fn halt_l(&self) -> bool
pub const fn halt_l(&self) -> bool
When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset.
Sourcepub const fn set_halt_l(&mut self, val: bool)
pub const fn set_halt_l(&mut self, val: bool)
When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset.
Sourcepub const fn clrctr_l(&self) -> bool
pub const fn clrctr_l(&self) -> bool
Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
Sourcepub const fn set_clrctr_l(&mut self, val: bool)
pub const fn set_clrctr_l(&mut self, val: bool)
Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
Sourcepub const fn set_bidir_l(&mut self, val: Bidir)
pub const fn set_bidir_l(&mut self, val: Bidir)
L or unified counter direction select
Sourcepub const fn pre_l(&self) -> u8
pub const fn pre_l(&self) -> u8
Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
Sourcepub const fn set_pre_l(&mut self, val: u8)
pub const fn set_pre_l(&mut self, val: u8)
Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
Sourcepub const fn down_h(&self) -> bool
pub const fn down_h(&self) -> bool
This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
Sourcepub const fn set_down_h(&mut self, val: bool)
pub const fn set_down_h(&mut self, val: bool)
This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
Sourcepub const fn stop_h(&self) -> bool
pub const fn stop_h(&self) -> bool
When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
Sourcepub const fn set_stop_h(&mut self, val: bool)
pub const fn set_stop_h(&mut self, val: bool)
When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
Sourcepub const fn halt_h(&self) -> bool
pub const fn halt_h(&self) -> bool
When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset.
Sourcepub const fn set_halt_h(&mut self, val: bool)
pub const fn set_halt_h(&mut self, val: bool)
When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset.
Sourcepub const fn clrctr_h(&self) -> bool
pub const fn clrctr_h(&self) -> bool
Writing a 1 to this bit clears the H counter. This bit always reads as 0.
Sourcepub const fn set_clrctr_h(&mut self, val: bool)
pub const fn set_clrctr_h(&mut self, val: bool)
Writing a 1 to this bit clears the H counter. This bit always reads as 0.
Sourcepub const fn set_bidir_h(&mut self, val: Bidir)
pub const fn set_bidir_h(&mut self, val: Bidir)
Direction select
Sourcepub const fn pre_h(&self) -> u8
pub const fn pre_h(&self) -> u8
Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
Sourcepub const fn set_pre_h(&mut self, val: u8)
pub const fn set_pre_h(&mut self, val: u8)
Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.