#[repr(transparent)]pub struct Dmareq0(pub u32);Expand description
SCT DMA request 0 register
Tuple Fields§
§0: u32Implementations§
Source§impl Dmareq0
impl Dmareq0
Sourcepub const fn dev_0(&self) -> u16
pub const fn dev_0(&self) -> u16
If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
Sourcepub const fn set_dev_0(&mut self, val: u16)
pub const fn set_dev_0(&mut self, val: u16)
If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
Sourcepub const fn drl0(&self) -> bool
pub const fn drl0(&self) -> bool
A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
Sourcepub const fn set_drl0(&mut self, val: bool)
pub const fn set_drl0(&mut self, val: bool)
A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
Sourcepub const fn drq0(&self) -> bool
pub const fn drq0(&self) -> bool
This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.
Sourcepub const fn set_drq0(&mut self, val: bool)
pub const fn set_drq0(&mut self, val: bool)
This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.