Module regs Copy item path Source Cfg SPI Configuration register Div SPI clock Divider Dly SPI Delay register Fifocfg FIFO configuration and enable register. Fifointenclr FIFO interrupt enable clear (disable) and read register. Fifointenset FIFO interrupt enable set (enable) and read register. Fifointstat FIFO interrupt status register. Fiford FIFO read data. Fifordnopop FIFO data read with no FIFO pop. Fifosize FIFO size register Fifostat FIFO status register. Fifotrig FIFO trigger settings for interrupt and DMA request. Fifowr FIFO write data. Id Peripheral identification register. Intenclr SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. Intenset SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. Intstat SPI Interrupt Status Stat SPI Status. Some status flags can be cleared by writing a 1 to that bit position.