Struct Div 

#[repr(transparent)]
pub struct Div(pub u32);

SPI clock Divider

Tuple Fields

0: u32

Implementations

impl Div

pub const fn divval(&self) -> u16

Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.

pub const fn set_divval(&mut self, val: u16)

Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.

Trait Implementations

impl Clone for Div

fn clone(&self) -> Div

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Div

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Div

fn default() -> Div

Returns the “default value” for a type.

impl PartialEq for Div

fn eq(&self, other: &Div) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Div

impl Eq for Div

impl StructuralPartialEq for Div