#[repr(transparent)]pub struct Sdioclkctrl(pub u32);Expand description
SDIO CCLKIN phase and delay control
Tuple Fields§
§0: u32Implementations§
Source§impl Sdioclkctrl
impl Sdioclkctrl
Sourcepub const fn cclk_drv_phase(&self) -> CclkDrvPhase
pub const fn cclk_drv_phase(&self) -> CclkDrvPhase
Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
Sourcepub const fn set_cclk_drv_phase(&mut self, val: CclkDrvPhase)
pub const fn set_cclk_drv_phase(&mut self, val: CclkDrvPhase)
Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
Sourcepub const fn cclk_sample_phase(&self) -> CclkSamplePhase
pub const fn cclk_sample_phase(&self) -> CclkSamplePhase
Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
Sourcepub const fn set_cclk_sample_phase(&mut self, val: CclkSamplePhase)
pub const fn set_cclk_sample_phase(&mut self, val: CclkSamplePhase)
Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
Sourcepub const fn phase_active(&self) -> PhaseActive
pub const fn phase_active(&self) -> PhaseActive
Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.
Sourcepub const fn set_phase_active(&mut self, val: PhaseActive)
pub const fn set_phase_active(&mut self, val: PhaseActive)
Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.
Sourcepub const fn cclk_drv_delay(&self) -> u8
pub const fn cclk_drv_delay(&self) -> u8
Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
Sourcepub const fn set_cclk_drv_delay(&mut self, val: u8)
pub const fn set_cclk_drv_delay(&mut self, val: u8)
Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
Sourcepub const fn cclk_drv_delay_active(&self) -> bool
pub const fn cclk_drv_delay_active(&self) -> bool
Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
Sourcepub const fn set_cclk_drv_delay_active(&mut self, val: bool)
pub const fn set_cclk_drv_delay_active(&mut self, val: bool)
Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
Sourcepub const fn cclk_sample_delay(&self) -> u8
pub const fn cclk_sample_delay(&self) -> u8
Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
Sourcepub const fn set_cclk_sample_delay(&mut self, val: u8)
pub const fn set_cclk_sample_delay(&mut self, val: u8)
Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
Sourcepub const fn cclk_sample_delay_active(&self) -> bool
pub const fn cclk_sample_delay_active(&self) -> bool
Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
Sourcepub const fn set_cclk_sample_delay_active(&mut self, val: bool)
pub const fn set_cclk_sample_delay_active(&mut self, val: bool)
Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
Trait Implementations§
Source§impl Clone for Sdioclkctrl
impl Clone for Sdioclkctrl
Source§fn clone(&self) -> Sdioclkctrl
fn clone(&self) -> Sdioclkctrl
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more