#[repr(transparent)]pub struct PllSic(pub u32);Expand description
USB PHY PLL Control/Status Register
Tuple Fields§
§0: u32Implementations§
Source§impl PllSic
impl PllSic
Sourcepub const fn pll_en_usb_clks(&self) -> bool
pub const fn pll_en_usb_clks(&self) -> bool
Enables the USB clock from PLL to USB PHY
Sourcepub const fn set_pll_en_usb_clks(&mut self, val: bool)
pub const fn set_pll_en_usb_clks(&mut self, val: bool)
Enables the USB clock from PLL to USB PHY
Sourcepub const fn set_pll_power(&mut self, val: bool)
pub const fn set_pll_power(&mut self, val: bool)
Power up the USB PLL
Sourcepub const fn pll_enable(&self) -> bool
pub const fn pll_enable(&self) -> bool
Enables the clock output from the USB PLL
Sourcepub const fn set_pll_enable(&mut self, val: bool)
pub const fn set_pll_enable(&mut self, val: bool)
Enables the clock output from the USB PLL
Sourcepub const fn refbias_pwd_sel(&self) -> PllSicRefbiasPwdSel
pub const fn refbias_pwd_sel(&self) -> PllSicRefbiasPwdSel
Reference bias power down select.
Sourcepub const fn set_refbias_pwd_sel(&mut self, val: PllSicRefbiasPwdSel)
pub const fn set_refbias_pwd_sel(&mut self, val: PllSicRefbiasPwdSel)
Reference bias power down select.
Sourcepub const fn refbias_pwd(&self) -> bool
pub const fn refbias_pwd(&self) -> bool
Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.
Sourcepub const fn set_refbias_pwd(&mut self, val: bool)
pub const fn set_refbias_pwd(&mut self, val: bool)
Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.
Sourcepub const fn pll_reg_enable(&self) -> bool
pub const fn pll_reg_enable(&self) -> bool
This field controls the USB PLL regulator, set to enable the regulator
Sourcepub const fn set_pll_reg_enable(&mut self, val: bool)
pub const fn set_pll_reg_enable(&mut self, val: bool)
This field controls the USB PLL regulator, set to enable the regulator
Sourcepub const fn pll_div_sel(&self) -> PllSicPllDivSel
pub const fn pll_div_sel(&self) -> PllSicPllDivSel
This field controls the USB PLL feedback loop divider
Sourcepub const fn set_pll_div_sel(&mut self, val: PllSicPllDivSel)
pub const fn set_pll_div_sel(&mut self, val: PllSicPllDivSel)
This field controls the USB PLL feedback loop divider
Sourcepub const fn pll_prediv(&self) -> bool
pub const fn pll_prediv(&self) -> bool
This is selection between /1 or /2 to expand the range of ref input clock.
Sourcepub const fn set_pll_prediv(&mut self, val: bool)
pub const fn set_pll_prediv(&mut self, val: bool)
This is selection between /1 or /2 to expand the range of ref input clock.
Sourcepub const fn pll_lock(&self) -> PllSicPllLock
pub const fn pll_lock(&self) -> PllSicPllLock
USB PLL lock status indicator
Sourcepub const fn set_pll_lock(&mut self, val: PllSicPllLock)
pub const fn set_pll_lock(&mut self, val: PllSicPllLock)
USB PLL lock status indicator