#[repr(u8)]pub enum Pwren {
PWREN_0 = 0,
PWREN_1 = 1,
}Variants§
PWREN_0 = 0
ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
PWREN_1 = 1
ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed.
Implementations§
Trait Implementations§
Source§impl Ord for Pwren
impl Ord for Pwren
Source§impl PartialOrd for Pwren
impl PartialOrd for Pwren
impl Copy for Pwren
impl Eq for Pwren
impl StructuralPartialEq for Pwren
Auto Trait Implementations§
impl Freeze for Pwren
impl RefUnwindSafe for Pwren
impl Send for Pwren
impl Sync for Pwren
impl Unpin for Pwren
impl UnwindSafe for Pwren
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more