pub struct AhbSecureCtrl { /* private fields */ }Expand description
AHB secure controller
Implementations§
Source§impl AhbSecureCtrl
impl AhbSecureCtrl
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self
pub const fn as_ptr(&self) -> *mut ()
Sourcepub const fn sec_ctrl_flash_rom_slave_rule(
self,
) -> Reg<SecCtrlFlashRomSlaveRule, RW>
pub const fn sec_ctrl_flash_rom_slave_rule( self, ) -> Reg<SecCtrlFlashRomSlaveRule, RW>
Security access rules for Flash and ROM slaves.
Sourcepub const fn sec_ctrl_flash_mem_rule0(self) -> Reg<SecCtrlFlashMemRule0, RW>
pub const fn sec_ctrl_flash_mem_rule0(self) -> Reg<SecCtrlFlashMemRule0, RW>
Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total.
Sourcepub const fn sec_ctrl_flash_mem_rule1(self) -> Reg<SecCtrlFlashMemRule1, RW>
pub const fn sec_ctrl_flash_mem_rule1(self) -> Reg<SecCtrlFlashMemRule1, RW>
Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total.
Sourcepub const fn sec_ctrl_flash_mem_rule2(self) -> Reg<SecCtrlFlashMemRule2, RW>
pub const fn sec_ctrl_flash_mem_rule2(self) -> Reg<SecCtrlFlashMemRule2, RW>
Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total.
Sourcepub const fn sec_ctrl_rom_mem_rule0(self) -> Reg<SecCtrlRomMemRule0, RW>
pub const fn sec_ctrl_rom_mem_rule0(self) -> Reg<SecCtrlRomMemRule0, RW>
Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
Sourcepub const fn sec_ctrl_rom_mem_rule1(self) -> Reg<SecCtrlRomMemRule1, RW>
pub const fn sec_ctrl_rom_mem_rule1(self) -> Reg<SecCtrlRomMemRule1, RW>
Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
Sourcepub const fn sec_ctrl_rom_mem_rule2(self) -> Reg<SecCtrlRomMemRule2, RW>
pub const fn sec_ctrl_rom_mem_rule2(self) -> Reg<SecCtrlRomMemRule2, RW>
Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
Sourcepub const fn sec_ctrl_rom_mem_rule3(self) -> Reg<SecCtrlRomMemRule3, RW>
pub const fn sec_ctrl_rom_mem_rule3(self) -> Reg<SecCtrlRomMemRule3, RW>
Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
Sourcepub const fn sec_ctrl_ramx_slave_rule(self) -> Reg<SecCtrlRamxSlaveRule, RW>
pub const fn sec_ctrl_ramx_slave_rule(self) -> Reg<SecCtrlRamxSlaveRule, RW>
Security access rules for RAMX slaves.
Sourcepub const fn sec_ctrl_ramx_mem_rule0(self) -> Reg<SecCtrlRamxMemRule0, RW>
pub const fn sec_ctrl_ramx_mem_rule0(self) -> Reg<SecCtrlRamxMemRule0, RW>
Security access rules for RAMX slaves.
Sourcepub const fn sec_ctrl_ram0_slave_rule(self) -> Reg<SecCtrlRam0SlaveRule, RW>
pub const fn sec_ctrl_ram0_slave_rule(self) -> Reg<SecCtrlRam0SlaveRule, RW>
Security access rules for RAM0 slaves.
Sourcepub const fn sec_ctrl_ram0_mem_rule0(self) -> Reg<SecCtrlRam0MemRule0, RW>
pub const fn sec_ctrl_ram0_mem_rule0(self) -> Reg<SecCtrlRam0MemRule0, RW>
Security access rules for RAM0 slaves.
Sourcepub const fn sec_ctrl_ram0_mem_rule1(self) -> Reg<SecCtrlRam0MemRule1, RW>
pub const fn sec_ctrl_ram0_mem_rule1(self) -> Reg<SecCtrlRam0MemRule1, RW>
Security access rules for RAM0 slaves.
Sourcepub const fn sec_ctrl_ram1_slave_rule(self) -> Reg<SecCtrlRam1SlaveRule, RW>
pub const fn sec_ctrl_ram1_slave_rule(self) -> Reg<SecCtrlRam1SlaveRule, RW>
Security access rules for RAM1 slaves.
Sourcepub const fn sec_ctrl_ram1_mem_rule0(self) -> Reg<SecCtrlRam1MemRule0, RW>
pub const fn sec_ctrl_ram1_mem_rule0(self) -> Reg<SecCtrlRam1MemRule0, RW>
Security access rules for RAM1 slaves.
Sourcepub const fn sec_ctrl_ram1_mem_rule1(self) -> Reg<SecCtrlRam1MemRule1, RW>
pub const fn sec_ctrl_ram1_mem_rule1(self) -> Reg<SecCtrlRam1MemRule1, RW>
Security access rules for RAM1 slaves.
Sourcepub const fn sec_ctrl_ram2_slave_rule(self) -> Reg<SecCtrlRam2SlaveRule, RW>
pub const fn sec_ctrl_ram2_slave_rule(self) -> Reg<SecCtrlRam2SlaveRule, RW>
Security access rules for RAM2 slaves.
Sourcepub const fn sec_ctrl_ram2_mem_rule0(self) -> Reg<SecCtrlRam2MemRule0, RW>
pub const fn sec_ctrl_ram2_mem_rule0(self) -> Reg<SecCtrlRam2MemRule0, RW>
Security access rules for RAM2 slaves.
Sourcepub const fn sec_ctrl_ram2_mem_rule1(self) -> Reg<SecCtrlRam2MemRule1, RW>
pub const fn sec_ctrl_ram2_mem_rule1(self) -> Reg<SecCtrlRam2MemRule1, RW>
Security access rules for RAM2 slaves.
Sourcepub const fn sec_ctrl_ram3_slave_rule(self) -> Reg<SecCtrlRam3SlaveRule, RW>
pub const fn sec_ctrl_ram3_slave_rule(self) -> Reg<SecCtrlRam3SlaveRule, RW>
Security access rules for RAM3 slaves.
Sourcepub const fn sec_ctrl_ram3_mem_rule0(self) -> Reg<SecCtrlRam3MemRule0, RW>
pub const fn sec_ctrl_ram3_mem_rule0(self) -> Reg<SecCtrlRam3MemRule0, RW>
Security access rules for RAM3 slaves.
Sourcepub const fn sec_ctrl_ram3_mem_rule1(self) -> Reg<SecCtrlRam3MemRule1, RW>
pub const fn sec_ctrl_ram3_mem_rule1(self) -> Reg<SecCtrlRam3MemRule1, RW>
Security access rules for RAM3 slaves.
Sourcepub const fn sec_ctrl_ram4_slave_rule(self) -> Reg<SecCtrlRam4SlaveRule, RW>
pub const fn sec_ctrl_ram4_slave_rule(self) -> Reg<SecCtrlRam4SlaveRule, RW>
Security access rules for RAM4 slaves.
Sourcepub const fn sec_ctrl_ram4_mem_rule0(self) -> Reg<SecCtrlRam4MemRule0, RW>
pub const fn sec_ctrl_ram4_mem_rule0(self) -> Reg<SecCtrlRam4MemRule0, RW>
Security access rules for RAM4 slaves.
Sourcepub const fn sec_ctrl_apb_bridge_slave_rule(
self,
) -> Reg<SecCtrlApbBridgeSlaveRule, RW>
pub const fn sec_ctrl_apb_bridge_slave_rule( self, ) -> Reg<SecCtrlApbBridgeSlaveRule, RW>
Security access rules for both APB Bridges slaves.
Sourcepub const fn sec_ctrl_apb_bridge0_mem_ctrl0(
self,
) -> Reg<SecCtrlApbBridge0MemCtrl0, RW>
pub const fn sec_ctrl_apb_bridge0_mem_ctrl0( self, ) -> Reg<SecCtrlApbBridge0MemCtrl0, RW>
Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.
Sourcepub const fn sec_ctrl_apb_bridge0_mem_ctrl1(
self,
) -> Reg<SecCtrlApbBridge0MemCtrl1, RW>
pub const fn sec_ctrl_apb_bridge0_mem_ctrl1( self, ) -> Reg<SecCtrlApbBridge0MemCtrl1, RW>
Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.
Sourcepub const fn sec_ctrl_apb_bridge0_mem_ctrl2(
self,
) -> Reg<SecCtrlApbBridge0MemCtrl2, RW>
pub const fn sec_ctrl_apb_bridge0_mem_ctrl2( self, ) -> Reg<SecCtrlApbBridge0MemCtrl2, RW>
Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.
Sourcepub const fn sec_ctrl_apb_bridge1_mem_ctrl0(
self,
) -> Reg<SecCtrlApbBridge1MemCtrl0, RW>
pub const fn sec_ctrl_apb_bridge1_mem_ctrl0( self, ) -> Reg<SecCtrlApbBridge1MemCtrl0, RW>
Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
Sourcepub const fn sec_ctrl_apb_bridge1_mem_ctrl1(
self,
) -> Reg<SecCtrlApbBridge1MemCtrl1, RW>
pub const fn sec_ctrl_apb_bridge1_mem_ctrl1( self, ) -> Reg<SecCtrlApbBridge1MemCtrl1, RW>
Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
Sourcepub const fn sec_ctrl_apb_bridge1_mem_ctrl2(
self,
) -> Reg<SecCtrlApbBridge1MemCtrl2, RW>
pub const fn sec_ctrl_apb_bridge1_mem_ctrl2( self, ) -> Reg<SecCtrlApbBridge1MemCtrl2, RW>
Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
Sourcepub const fn sec_ctrl_apb_bridge1_mem_ctrl3(
self,
) -> Reg<SecCtrlApbBridge1MemCtrl3, RW>
pub const fn sec_ctrl_apb_bridge1_mem_ctrl3( self, ) -> Reg<SecCtrlApbBridge1MemCtrl3, RW>
Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
Sourcepub const fn sec_ctrl_ahb_port8_slave0_rule(
self,
) -> Reg<SecCtrlAhbPort8Slave0Rule, RW>
pub const fn sec_ctrl_ahb_port8_slave0_rule( self, ) -> Reg<SecCtrlAhbPort8Slave0Rule, RW>
Security access rules for AHB peripherals.
Sourcepub const fn sec_ctrl_ahb_port8_slave1_rule(
self,
) -> Reg<SecCtrlAhbPort8Slave1Rule, RW>
pub const fn sec_ctrl_ahb_port8_slave1_rule( self, ) -> Reg<SecCtrlAhbPort8Slave1Rule, RW>
Security access rules for AHB peripherals.
Sourcepub const fn sec_ctrl_ahb_port9_slave0_rule(
self,
) -> Reg<SecCtrlAhbPort9Slave0Rule, RW>
pub const fn sec_ctrl_ahb_port9_slave0_rule( self, ) -> Reg<SecCtrlAhbPort9Slave0Rule, RW>
Security access rules for AHB peripherals.
Sourcepub const fn sec_ctrl_ahb_port9_slave1_rule(
self,
) -> Reg<SecCtrlAhbPort9Slave1Rule, RW>
pub const fn sec_ctrl_ahb_port9_slave1_rule( self, ) -> Reg<SecCtrlAhbPort9Slave1Rule, RW>
Security access rules for AHB peripherals.
Sourcepub const fn sec_ctrl_ahb_port10_slave0_rule(
self,
) -> Reg<SecCtrlAhbPort10Slave0Rule, RW>
pub const fn sec_ctrl_ahb_port10_slave0_rule( self, ) -> Reg<SecCtrlAhbPort10Slave0Rule, RW>
Security access rules for AHB peripherals.
Sourcepub const fn sec_ctrl_ahb_port10_slave1_rule(
self,
) -> Reg<SecCtrlAhbPort10Slave1Rule, RW>
pub const fn sec_ctrl_ahb_port10_slave1_rule( self, ) -> Reg<SecCtrlAhbPort10Slave1Rule, RW>
Security access rules for AHB peripherals.
Sourcepub const fn sec_ctrl_ahb_sec_ctrl_mem_rule(
self,
) -> Reg<SecCtrlAhbSecCtrlMemRule, RW>
pub const fn sec_ctrl_ahb_sec_ctrl_mem_rule( self, ) -> Reg<SecCtrlAhbSecCtrlMemRule, RW>
Security access rules for AHB_SEC_CTRL_AHB.
Sourcepub const fn sec_ctrl_usb_hs_slave_rule(self) -> Reg<SecCtrlUsbHsSlaveRule, RW>
pub const fn sec_ctrl_usb_hs_slave_rule(self) -> Reg<SecCtrlUsbHsSlaveRule, RW>
Security access rules for USB High speed RAM slaves.
Sourcepub const fn sec_ctrl_usb_hs_mem_rule(self) -> Reg<SecCtrlUsbHsMemRule, RW>
pub const fn sec_ctrl_usb_hs_mem_rule(self) -> Reg<SecCtrlUsbHsMemRule, RW>
Security access rules for RAM_USB_HS.
Sourcepub const fn sec_vio_addr(self, n: usize) -> Reg<SecVioAddr, R>
pub const fn sec_vio_addr(self, n: usize) -> Reg<SecVioAddr, R>
most recent security violation address for AHB port n
Sourcepub const fn sec_vio_misc_info(self, n: usize) -> Reg<SecVioMiscInfo, R>
pub const fn sec_vio_misc_info(self, n: usize) -> Reg<SecVioMiscInfo, R>
most recent security violation miscellaneous information for AHB port n
Sourcepub const fn sec_vio_info_valid(self) -> Reg<SecVioInfoValid, RW>
pub const fn sec_vio_info_valid(self) -> Reg<SecVioInfoValid, RW>
security violation address/information registers valid flags
Sourcepub const fn sec_gpio_mask0(self) -> Reg<SecGpioMask0, RW>
pub const fn sec_gpio_mask0(self) -> Reg<SecGpioMask0, RW>
Secure GPIO mask for port 0 pins.
Sourcepub const fn sec_gpio_mask1(self) -> Reg<SecGpioMask1, RW>
pub const fn sec_gpio_mask1(self) -> Reg<SecGpioMask1, RW>
Secure GPIO mask for port 1 pins.
Sourcepub const fn sec_cpu_int_mask0(self) -> Reg<SecCpuIntMask0, RW>
pub const fn sec_cpu_int_mask0(self) -> Reg<SecCpuIntMask0, RW>
Secure Interrupt mask for CPU1
Sourcepub const fn sec_cpu_int_mask1(self) -> Reg<SecCpuIntMask1, RW>
pub const fn sec_cpu_int_mask1(self) -> Reg<SecCpuIntMask1, RW>
Secure Interrupt mask for CPU1
Sourcepub const fn sec_mask_lock(self) -> Reg<SecMaskLock, RW>
pub const fn sec_mask_lock(self) -> Reg<SecMaskLock, RW>
Security General Purpose register access control.
Sourcepub const fn master_sec_level(self) -> Reg<MasterSecLevel, RW>
pub const fn master_sec_level(self) -> Reg<MasterSecLevel, RW>
master secure level register
Sourcepub const fn master_sec_anti_pol_reg(self) -> Reg<MasterSecAntiPolReg, RW>
pub const fn master_sec_anti_pol_reg(self) -> Reg<MasterSecAntiPolReg, RW>
master secure level anti-pole register
Sourcepub const fn cpu0_lock_reg(self) -> Reg<Cpu0LockReg, RW>
pub const fn cpu0_lock_reg(self) -> Reg<Cpu0LockReg, RW>
Miscalleneous control signals for in Cortex M33 (CPU0)
Sourcepub const fn cpu1_lock_reg(self) -> Reg<Cpu1LockReg, RW>
pub const fn cpu1_lock_reg(self) -> Reg<Cpu1LockReg, RW>
Miscalleneous control signals for in micro-Cortex M33 (CPU1)
Sourcepub const fn misc_ctrl_dp_reg(self) -> Reg<MiscCtrlDpReg, RW>
pub const fn misc_ctrl_dp_reg(self) -> Reg<MiscCtrlDpReg, RW>
secure control duplicate register
Sourcepub const fn misc_ctrl_reg(self) -> Reg<MiscCtrlReg, RW>
pub const fn misc_ctrl_reg(self) -> Reg<MiscCtrlReg, RW>
secure control register
Trait Implementations§
Source§impl Clone for AhbSecureCtrl
impl Clone for AhbSecureCtrl
Source§fn clone(&self) -> AhbSecureCtrl
fn clone(&self) -> AhbSecureCtrl
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more