Struct Ctcr 

#[repr(transparent)]
pub struct Ctcr(pub u32);

Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

Tuple Fields

0: u32

Implementations

impl Ctcr

pub const fn ctmode(&self) -> Ctmode

Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.

pub const fn set_ctmode(&mut self, val: Ctmode)

Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.

pub const fn cinsel(&self) -> Cinsel

Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.

pub const fn set_cinsel(&mut self, val: Cinsel)

Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.

pub const fn encc(&self) -> bool

Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.

pub const fn set_encc(&mut self, val: bool)

Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.

pub const fn selcc(&self) -> Selcc

Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.

pub const fn set_selcc(&mut self, val: Selcc)

Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.

Trait Implementations

impl Clone for Ctcr

fn clone(&self) -> Ctcr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Ctcr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Ctcr

fn default() -> Ctcr

Returns the “default value” for a type.

impl PartialEq for Ctcr

fn eq(&self, other: &Ctcr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Ctcr

impl Eq for Ctcr

impl StructuralPartialEq for Ctcr