Struct Cfg1 

#[repr(transparent)]
pub struct Cfg1(pub u32);

Configuration register 1 for the primary channel pair.

Tuple Fields

0: u32

Implementations

impl Cfg1

pub const fn mainenable(&self) -> bool

Main enable for I 2S function in this Flexcomm

pub const fn set_mainenable(&mut self, val: bool)

Main enable for I 2S function in this Flexcomm

pub const fn datapause(&self) -> Datapause

Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame.

pub const fn set_datapause(&mut self, val: Datapause)

Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame.

pub const fn paircount(&self) -> Paircount

Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm.

pub const fn set_paircount(&mut self, val: Paircount)

Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm.

pub const fn mstslvcfg(&self) -> Mstslvcfg

Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.

pub const fn set_mstslvcfg(&mut self, val: Mstslvcfg)

Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.

pub const fn mode(&self) -> Mode

Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples.

pub const fn set_mode(&mut self, val: Mode)

Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples.

pub const fn rightlow(&self) -> Rightlow

Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed.

pub const fn set_rightlow(&mut self, val: Rightlow)

Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed.

pub const fn leftjust(&self) -> Leftjust

Left Justify data.

pub const fn set_leftjust(&mut self, val: Leftjust)

Left Justify data.

pub const fn onechannel(&self) -> Onechannel

Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers.

pub const fn set_onechannel(&mut self, val: Onechannel)

Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers.

pub const fn sck_pol(&self) -> SckPol

SCK polarity.

pub const fn set_sck_pol(&mut self, val: SckPol)

SCK polarity.

pub const fn ws_pol(&self) -> bool

WS polarity.

pub const fn set_ws_pol(&mut self, val: bool)

WS polarity.

pub const fn datalen(&self) -> u8

Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length

pub const fn set_datalen(&mut self, val: u8)

Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length

Trait Implementations

impl Clone for Cfg1

fn clone(&self) -> Cfg1

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Cfg1

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Cfg1

fn default() -> Cfg1

Returns the “default value” for a type.

impl PartialEq for Cfg1

fn eq(&self, other: &Cfg1) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cfg1

impl Eq for Cfg1

impl StructuralPartialEq for Cfg1