Module mrcc 

Peripheral access API (generated using chiptool v0.1.0 (e5ab29f 2026-04-30))

Structs

Mrcc

MRCC.

MrccAdc0Clkdiv

ADC0 clock divider control.

MrccAdc0Clksel

ADC0 clock selection control.

MrccAdc1Clkdiv

ADC1 clock divider control.

MrccAdc1Clksel

ADC1 clock selection control.

MrccClkoutClkdiv

CLKOUT clock divider control.

MrccClkoutClksel

CLKOUT clock selection control.

MrccCmp0FuncClkdiv

CMP0_FUNC clock divider control.

MrccCmp0RrClkdiv

CMP0_RR clock divider control.

MrccCmp0RrClksel

CMP0_RR clock selection control.

MrccCmp1FuncClkdiv

CMP1_FUNC clock divider control.

MrccCmp1RrClkdiv

CMP1_RR clock divider control.

MrccCmp1RrClksel

CMP1_RR clock selection control.

MrccCtimer0Clkdiv

CTIMER0 clock divider control.

MrccCtimer0Clksel

CTIMER0 clock selection control.

MrccCtimer1Clkdiv

CTIMER1 clock divider control.

MrccCtimer1Clksel

CTIMER1 clock selection control.

MrccCtimer2Clkdiv

CTIMER2 clock divider control.

MrccCtimer2Clksel

CTIMER2 clock selection control.

MrccCtimer3Clkdiv

CTIMER3 clock divider control.

MrccCtimer3Clksel

CTIMER3 clock selection control.

MrccCtimer4Clkdiv

CTIMER4 clock divider control.

MrccCtimer4Clksel

CTIMER4 clock selection control.

MrccDac0Clkdiv

DAC0 clock divider control.

MrccDac0Clksel

DAC0 clock selection control.

MrccDbgTraceClkdiv

DBG_TRACE clock divider control.

MrccDbgTraceClksel

DBG_TRACE clock selection control.

MrccFlexcan0Clkdiv

FLEXCAN0 clock divider control.

MrccFlexcan0Clksel

FLEXCAN0 clock selection control.

MrccFlexio0Clkdiv

FLEXIO0 clock divider control.

MrccFlexio0Clksel

FLEXIO0 clock selection control.

MrccFroHfDivClkdiv

FRO_HF_DIV clock divider control.

MrccGlbAcc0

Control Automatic Clock Gating 0.

MrccGlbAcc1

Control Automatic Clock Gating 1.

MrccGlbCc0

AHB Clock Control 0.

MrccGlbCc0Clr

AHB Clock Control Clear 0.

MrccGlbCc0Set

AHB Clock Control Set 0.

MrccGlbCc1

AHB Clock Control 1.

MrccGlbCc1Clr

AHB Clock Control Clear 1.

MrccGlbCc1Set

AHB Clock Control Set 1.

MrccGlbRst0

Peripheral Reset Control 0.

MrccGlbRst0Clr

Peripheral Reset Control Clear 0.

MrccGlbRst0Set

Peripheral Reset Control Set 0.

MrccGlbRst1

Peripheral Reset Control 1.

MrccGlbRst1Clr

Peripheral Reset Control Clear 1.

MrccGlbRst1Set

Peripheral Reset Control Set 1.

MrccI3c0FclkClkdiv

I3C0_FCLK clock divider control.

MrccI3c0FclkClksel

I3C0_FCLK clock selection control.

MrccLpi2c0Clkdiv

LPI2C0 clock divider control.

MrccLpi2c0Clksel

LPI2C0 clock selection control.

MrccLpi2c1Clkdiv

LPI2C1 clock divider control.

MrccLpi2c1Clksel

LPI2C1 clock selection control.

MrccLpi2c2Clkdiv

LPI2C2 clock divider control.

MrccLpi2c2Clksel

LPI2C2 clock selection control.

MrccLpi2c3Clkdiv

LPI2C3 clock divider control.

MrccLpi2c3Clksel

LPI2C3 clock selection control.

MrccLpspi0Clkdiv

LPSPI0 clock divider control.

MrccLpspi0Clksel

LPSPI0 clock selection control.

MrccLpspi1Clkdiv

LPSPI1 clock divider control.

MrccLpspi1Clksel

LPSPI1 clock selection control.

MrccLptmr0Clkdiv

LPTMR0 clock divider control.

MrccLptmr0Clksel

LPTMR0 clock selection control.

MrccLpuart0Clkdiv

LPUART0 clock divider control.

MrccLpuart0Clksel

LPUART0 clock selection control.

MrccLpuart1Clkdiv

LPUART1 clock divider control.

MrccLpuart1Clksel

LPUART1 clock selection control.

MrccLpuart2Clkdiv

LPUART2 clock divider control.

MrccLpuart2Clksel

LPUART2 clock selection control.

MrccLpuart3Clkdiv

LPUART3 clock divider control.

MrccLpuart3Clksel

LPUART3 clock selection control.

MrccLpuart4Clkdiv

LPUART4 clock divider control.

MrccLpuart4Clksel

LPUART4 clock selection control.

MrccOstimer0Clksel

OSTIMER0 clock selection control.

MrccSystickClkdiv

SYSTICK clock divider control.

MrccSystickClksel

SYSTICK clock selection control.

MrccUsb0Clksel

USB0 clock selection control.

MrccWwdt0Clkdiv

WWDT0 clock divider control.

Enums

MrccAdc0ClkdivHalt

MrccAdc0ClkdivReset

MrccAdc0ClkdivUnstab

MrccAdc0ClkselMux

MrccAdc1ClkdivHalt

MrccAdc1ClkdivReset

MrccAdc1ClkdivUnstab

MrccAdc1ClkselMux

MrccClkoutClkdivHalt

MrccClkoutClkdivReset

MrccClkoutClkdivUnstab

MrccClkoutClkselMux

MrccCmp0FuncClkdivHalt

MrccCmp0FuncClkdivReset

MrccCmp0FuncClkdivUnstab

MrccCmp0RrClkdivHalt

MrccCmp0RrClkdivReset

MrccCmp0RrClkdivUnstab

MrccCmp0RrClkselMux

MrccCmp1FuncClkdivHalt

MrccCmp1FuncClkdivReset

MrccCmp1FuncClkdivUnstab

MrccCmp1RrClkdivHalt

MrccCmp1RrClkdivReset

MrccCmp1RrClkdivUnstab

MrccCmp1RrClkselMux

MrccCtimer0ClkdivHalt

MrccCtimer0ClkdivReset

MrccCtimer0ClkdivUnstab

MrccCtimer0ClkselMux

MrccCtimer1ClkdivHalt

MrccCtimer1ClkdivReset

MrccCtimer1ClkdivUnstab

MrccCtimer1ClkselMux

MrccCtimer2ClkdivHalt

MrccCtimer2ClkdivReset

MrccCtimer2ClkdivUnstab

MrccCtimer2ClkselMux

MrccCtimer3ClkdivHalt

MrccCtimer3ClkdivReset

MrccCtimer3ClkdivUnstab

MrccCtimer3ClkselMux

MrccCtimer4ClkdivHalt

MrccCtimer4ClkdivReset

MrccCtimer4ClkdivUnstab

MrccCtimer4ClkselMux

MrccDac0ClkdivHalt

MrccDac0ClkdivReset

MrccDac0ClkdivUnstab

MrccDac0ClkselMux

MrccDbgTraceClkdivHalt

MrccDbgTraceClkdivReset

MrccDbgTraceClkdivUnstab

MrccDbgTraceClkselMux

MrccFlexcan0ClkdivHalt

MrccFlexcan0ClkdivReset

MrccFlexcan0ClkdivUnstab

MrccFlexcan0ClkselMux

MrccFlexio0ClkdivHalt

MrccFlexio0ClkdivReset

MrccFlexio0ClkdivUnstab

MrccFlexio0ClkselMux

MrccFroHfDivClkdivUnstab

MrccI3c0FclkClkdivHalt

MrccI3c0FclkClkdivReset

MrccI3c0FclkClkdivUnstab

MrccI3c0FclkClkselMux

MrccLpi2c0ClkdivHalt

MrccLpi2c0ClkdivReset

MrccLpi2c0ClkdivUnstab

MrccLpi2c0ClkselMux

MrccLpi2c1ClkdivHalt

MrccLpi2c1ClkdivReset

MrccLpi2c1ClkdivUnstab

MrccLpi2c1ClkselMux

MrccLpi2c2ClkdivHalt

MrccLpi2c2ClkdivReset

MrccLpi2c2ClkdivUnstab

MrccLpi2c2ClkselMux

MrccLpi2c3ClkdivHalt

MrccLpi2c3ClkdivReset

MrccLpi2c3ClkdivUnstab

MrccLpi2c3ClkselMux

MrccLpspi0ClkdivHalt

MrccLpspi0ClkdivReset

MrccLpspi0ClkdivUnstab

MrccLpspi0ClkselMux

MrccLpspi1ClkdivHalt

MrccLpspi1ClkdivReset

MrccLpspi1ClkdivUnstab

MrccLpspi1ClkselMux

MrccLptmr0ClkdivHalt

MrccLptmr0ClkdivReset

MrccLptmr0ClkdivUnstab

MrccLptmr0ClkselMux

MrccLpuart0ClkdivHalt

MrccLpuart0ClkdivReset

MrccLpuart0ClkdivUnstab

MrccLpuart0ClkselMux

MrccLpuart1ClkdivHalt

MrccLpuart1ClkdivReset

MrccLpuart1ClkdivUnstab

MrccLpuart1ClkselMux

MrccLpuart2ClkdivHalt

MrccLpuart2ClkdivReset

MrccLpuart2ClkdivUnstab

MrccLpuart2ClkselMux

MrccLpuart3ClkdivHalt

MrccLpuart3ClkdivReset

MrccLpuart3ClkdivUnstab

MrccLpuart3ClkselMux

MrccLpuart4ClkdivHalt

MrccLpuart4ClkdivReset

MrccLpuart4ClkdivUnstab

MrccLpuart4ClkselMux

MrccOstimer0ClkselMux

MrccSystickClkdivHalt

MrccSystickClkdivReset

MrccSystickClkdivUnstab

MrccSystickClkselMux

MrccUsb0ClkselMux

MrccWwdt0ClkdivHalt

MrccWwdt0ClkdivReset

MrccWwdt0ClkdivUnstab