Module mrcc 

Peripheral access API (generated using chiptool v0.1.0 (e890244 2026-11-05))

Structs

Mrcc

MRCC.

MrccAdcClkdiv

ADCx clock divider control.

MrccAdcClksel

ADCx clock selection control.

MrccClkoutClkdiv

CLKOUT clock divider control.

MrccClkoutClksel

CLKOUT clock selection control.

MrccCmp0FuncClkdiv

CMP0_FUNC clock divider control.

MrccCmp0RrClkdiv

CMP0_RR clock divider control.

MrccCmp0RrClksel

CMP0_RR clock selection control.

MrccCmp1FuncClkdiv

CMP1_FUNC clock divider control.

MrccCmp1RrClkdiv

CMP1_RR clock divider control.

MrccCmp1RrClksel

CMP1_RR clock selection control.

MrccCtimer0Clkdiv

CTIMER0 clock divider control.

MrccCtimer0Clksel

CTIMER0 clock selection control.

MrccCtimer1Clkdiv

CTIMER1 clock divider control.

MrccCtimer1Clksel

CTIMER1 clock selection control.

MrccCtimer2Clkdiv

CTIMER2 clock divider control.

MrccCtimer2Clksel

CTIMER2 clock selection control.

MrccDbgTraceClkdiv

DBG_TRACE clock divider control.

MrccDbgTraceClksel

DBG_TRACE clock selection control.

MrccFlexcan0Clkdiv

FLEXCAN0 clock divider control.

MrccFlexcan0Clksel

FLEXCAN0 clock selection control.

MrccGlbAcc0

Control Automatic Clock Gating 0.

MrccGlbAcc1

Control Automatic Clock Gating 1.

MrccGlbAcc2

Control Automatic Clock Gating 2.

MrccGlbCc0

AHB Clock Control 0.

MrccGlbCc0Clr

AHB Clock Control Clear 0.

MrccGlbCc0Set

AHB Clock Control Set 0.

MrccGlbCc1

AHB Clock Control 1.

MrccGlbCc2

AHB Clock Control 2.

MrccGlbCc1Clr

AHB Clock Control Clear 1.

MrccGlbCc1Set

AHB Clock Control Set 1.

MrccGlbCc2Clr

AHB Clock Control Clear 2.

MrccGlbCc2Set

AHB Clock Control Set 2.

MrccGlbRst0

Peripheral Reset Control 0.

MrccGlbRst0Clr

Peripheral Reset Control Clear 0.

MrccGlbRst0Set

Peripheral Reset Control Set 0.

MrccGlbRst1

Peripheral Reset Control 1.

MrccGlbRst2

Peripheral Reset Control 2.

MrccGlbRst1Clr

Peripheral Reset Control Clear 1.

MrccGlbRst1Set

Peripheral Reset Control Set 1.

MrccGlbRst2Clr

Peripheral Reset Control Clear 2.

MrccGlbRst2Set

Peripheral Reset Control Set 2.

MrccLpi2c0Clkdiv

LPI2C0 clock divider control.

MrccLpi2c0Clksel

LPI2C0 clock selection control.

MrccLpi2c1Clkdiv

LPI2C1 clock divider control.

MrccLpi2c1Clksel

LPI2C1 clock selection control.

MrccLpspi0Clkdiv

LPSPI0 clock divider control.

MrccLpspi0Clksel

LPSPI0 clock selection control.

MrccLpspi1Clkdiv

LPSPI1 clock divider control.

MrccLpspi1Clksel

LPSPI1 clock selection control.

MrccLptmr0Clkdiv

LPTMR0 clock divider control.

MrccLptmr0Clksel

LPTMR0 clock selection control.

MrccLpuart0Clkdiv

LPUART0 clock divider control.

MrccLpuart0Clksel

LPUART0 clock selection control.

MrccLpuart1Clkdiv

LPUART1 clock divider control.

MrccLpuart1Clksel

LPUART1 clock selection control.

MrccLpuart2Clkdiv

LPUART2 clock divider control.

MrccLpuart2Clksel

LPUART2 clock selection control.

MrccLpuart3Clkdiv

LPUART3 clock divider control.

MrccLpuart3Clksel

LPUART3 clock selection control.

MrccOstimer0Clksel

OSTIMER0 clock selection control.

MrccWwdt0Clkdiv

WWDT0 clock divider control.

Enums

MrccAdcClkdivHalt

MrccAdcClkdivReset

MrccAdcClkdivUnstab

MrccAdcClkselMux

MrccClkoutClkdivHalt

MrccClkoutClkdivReset

MrccClkoutClkdivUnstab

MrccClkoutClkselMux

MrccCmp0FuncClkdivHalt

MrccCmp0FuncClkdivReset

MrccCmp0FuncClkdivUnstab

MrccCmp0RrClkdivHalt

MrccCmp0RrClkdivReset

MrccCmp0RrClkdivUnstab

MrccCmp0RrClkselMux

MrccCmp1FuncClkdivHalt

MrccCmp1FuncClkdivReset

MrccCmp1FuncClkdivUnstab

MrccCmp1RrClkdivHalt

MrccCmp1RrClkdivReset

MrccCmp1RrClkdivUnstab

MrccCmp1RrClkselMux

MrccCtimer0ClkdivHalt

MrccCtimer0ClkdivReset

MrccCtimer0ClkdivUnstab

MrccCtimer0ClkselMux

MrccCtimer1ClkdivHalt

MrccCtimer1ClkdivReset

MrccCtimer1ClkdivUnstab

MrccCtimer1ClkselMux

MrccCtimer2ClkdivHalt

MrccCtimer2ClkdivReset

MrccCtimer2ClkdivUnstab

MrccCtimer2ClkselMux

MrccDbgTraceClkdivHalt

MrccDbgTraceClkdivReset

MrccDbgTraceClkdivUnstab

MrccDbgTraceClkselMux

MrccFlexcan0ClkdivHalt

MrccFlexcan0ClkdivReset

MrccFlexcan0ClkdivUnstab

MrccFlexcan0ClkselMux

MrccLpi2c0ClkdivHalt

MrccLpi2c0ClkdivReset

MrccLpi2c0ClkdivUnstab

MrccLpi2c0ClkselMux

MrccLpi2c1ClkdivHalt

MrccLpi2c1ClkdivReset

MrccLpi2c1ClkdivUnstab

MrccLpi2c1ClkselMux

MrccLpspi0ClkdivHalt

MrccLpspi0ClkdivReset

MrccLpspi0ClkdivUnstab

MrccLpspi0ClkselMux

MrccLpspi1ClkdivHalt

MrccLpspi1ClkdivReset

MrccLpspi1ClkdivUnstab

MrccLpspi1ClkselMux

MrccLptmr0ClkdivHalt

MrccLptmr0ClkdivReset

MrccLptmr0ClkdivUnstab

MrccLptmr0ClkselMux

MrccLpuart0ClkdivHalt

MrccLpuart0ClkdivReset

MrccLpuart0ClkdivUnstab

MrccLpuart0ClkselMux

MrccLpuart1ClkdivHalt

MrccLpuart1ClkdivReset

MrccLpuart1ClkdivUnstab

MrccLpuart1ClkselMux

MrccLpuart2ClkdivHalt

MrccLpuart2ClkdivReset

MrccLpuart2ClkdivUnstab

MrccLpuart2ClkselMux

MrccLpuart3ClkdivHalt

MrccLpuart3ClkdivReset

MrccLpuart3ClkdivUnstab

MrccLpuart3ClkselMux

MrccOstimer0ClkselMux

MrccWwdt0ClkdivHalt

MrccWwdt0ClkdivReset

MrccWwdt0ClkdivUnstab