Struct Flexpwm 

pub struct Flexpwm { /* private fields */ }

PWM

Implementations

impl Flexpwm

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn sm0cnt(self) -> Reg<Smcnt, R>

Counter Register

pub const fn sm0init(self) -> Reg<Sminit, RW>

Initial Count Register

pub const fn sm0ctrl2(self) -> Reg<Smctrl2, RW>

Control 2 Register

pub const fn sm0ctrl(self) -> Reg<Smctrl, RW>

Control Register

pub const fn sm0val(self, n: usize) -> Reg<Smval, RW>

Value Register 0

pub const fn sm0octrl(self) -> Reg<Smoctrl, RW>

Output Control Register

pub const fn sm0sts(self) -> Reg<Smsts, RW>

Status Register

pub const fn sm0inten(self) -> Reg<Sminten, RW>

Interrupt Enable Register

pub const fn sm0dmaen(self) -> Reg<Smdmaen, RW>

DMA Enable Register

pub const fn sm0tctrl(self) -> Reg<Smtctrl, RW>

Output Trigger Control Register

pub const fn sm0dismap0(self) -> Reg<Smdismap0, RW>

Fault Disable Mapping Register 0

pub const fn sm0dtcnt0(self) -> Reg<Smdtcnt0, RW>

Deadtime Count Register 0

pub const fn sm0dtcnt1(self) -> Reg<Smdtcnt1, RW>

Deadtime Count Register 1

pub const fn sm0captctrlx(self) -> Reg<Smcaptctrlx, RW>

Capture Control X Register

pub const fn sm0captcompx(self) -> Reg<Smcaptcompx, RW>

Capture Compare X Register

pub const fn sm0cval0(self) -> Reg<Smcval0, R>

Capture Value 0 Register

pub const fn sm0cval0cyc(self) -> Reg<Smcval0cyc, R>

Capture Value 0 Cycle Register

pub const fn sm0cval1(self) -> Reg<Smcval1, R>

Capture Value 1 Register

pub const fn sm0cval1cyc(self) -> Reg<Smcval1cyc, R>

Capture Value 1 Cycle Register

pub const fn sm0captfiltx(self) -> Reg<Smcaptfiltx, RW>

Capture PWM_X Input Filter Register

pub const fn sm1cnt(self) -> Reg<Smcnt, R>

Counter Register

pub const fn sm1init(self) -> Reg<Sminit, RW>

Initial Count Register

pub const fn sm1ctrl2(self) -> Reg<Smctrl2, RW>

Control 2 Register

pub const fn sm1ctrl(self) -> Reg<Smctrl, RW>

Control Register

pub const fn sm1val(self, n: usize) -> Reg<Smval, RW>

Value Register 0

pub const fn sm1octrl(self) -> Reg<Smoctrl, RW>

Output Control Register

pub const fn sm1sts(self) -> Reg<Smsts, RW>

Status Register

pub const fn sm1inten(self) -> Reg<Sminten, RW>

Interrupt Enable Register

pub const fn sm1dmaen(self) -> Reg<Smdmaen, RW>

DMA Enable Register

pub const fn sm1tctrl(self) -> Reg<Smtctrl, RW>

Output Trigger Control Register

pub const fn sm1dismap0(self) -> Reg<Smdismap0, RW>

Fault Disable Mapping Register 0

pub const fn sm1dtcnt0(self) -> Reg<Smdtcnt0, RW>

Deadtime Count Register 0

pub const fn sm1dtcnt1(self) -> Reg<Smdtcnt1, RW>

Deadtime Count Register 1

pub const fn sm1captctrlx(self) -> Reg<Smcaptctrlx, RW>

Capture Control X Register

pub const fn sm1captcompx(self) -> Reg<Smcaptcompx, RW>

Capture Compare X Register

pub const fn sm1cval0(self) -> Reg<Smcval0, R>

Capture Value 0 Register

pub const fn sm1cval0cyc(self) -> Reg<Smcval0cyc, R>

Capture Value 0 Cycle Register

pub const fn sm1cval1(self) -> Reg<Smcval1, R>

Capture Value 1 Register

pub const fn sm1cval1cyc(self) -> Reg<Smcval1cyc, R>

Capture Value 1 Cycle Register

pub const fn sm1phasedly(self) -> Reg<Smphasedly, RW>

Phase Delay Register

pub const fn sm1captfiltx(self) -> Reg<Smcaptfiltx, RW>

Capture PWM_X Input Filter Register

pub const fn sm2cnt(self) -> Reg<Smcnt, R>

Counter Register

pub const fn sm2init(self) -> Reg<Sminit, RW>

Initial Count Register

pub const fn sm2ctrl2(self) -> Reg<Smctrl2, RW>

Control 2 Register

pub const fn sm2ctrl(self) -> Reg<Smctrl, RW>

Control Register

pub const fn sm2val(self, n: usize) -> Reg<Smval, RW>

Value Register 0

pub const fn sm2octrl(self) -> Reg<Smoctrl, RW>

Output Control Register

pub const fn sm2sts(self) -> Reg<Smsts, RW>

Status Register

pub const fn sm2inten(self) -> Reg<Sminten, RW>

Interrupt Enable Register

pub const fn sm2dmaen(self) -> Reg<Smdmaen, RW>

DMA Enable Register

pub const fn sm2tctrl(self) -> Reg<Smtctrl, RW>

Output Trigger Control Register

pub const fn sm2dismap0(self) -> Reg<Smdismap0, RW>

Fault Disable Mapping Register 0

pub const fn sm2dtcnt0(self) -> Reg<Smdtcnt0, RW>

Deadtime Count Register 0

pub const fn sm2dtcnt1(self) -> Reg<Smdtcnt1, RW>

Deadtime Count Register 1

pub const fn sm2captctrlx(self) -> Reg<Smcaptctrlx, RW>

Capture Control X Register

pub const fn sm2captcompx(self) -> Reg<Smcaptcompx, RW>

Capture Compare X Register

pub const fn sm2cval0(self) -> Reg<Smcval0, R>

Capture Value 0 Register

pub const fn sm2cval0cyc(self) -> Reg<Smcval0cyc, R>

Capture Value 0 Cycle Register

pub const fn sm2cval1(self) -> Reg<Smcval1, R>

Capture Value 1 Register

pub const fn sm2cval1cyc(self) -> Reg<Smcval1cyc, R>

Capture Value 1 Cycle Register

pub const fn sm2phasedly(self) -> Reg<Smphasedly, RW>

Phase Delay Register

pub const fn sm2captfiltx(self) -> Reg<Smcaptfiltx, RW>

Capture PWM_X Input Filter Register

pub const fn sm3cnt(self) -> Reg<Smcnt, R>

Counter Register

pub const fn sm3init(self) -> Reg<Sminit, RW>

Initial Count Register

pub const fn sm3ctrl2(self) -> Reg<Smctrl2, RW>

Control 2 Register

pub const fn sm3ctrl(self) -> Reg<Smctrl, RW>

Control Register

pub const fn sm3val(self, n: usize) -> Reg<Smval, RW>

Value Register 0

pub const fn sm3octrl(self) -> Reg<Smoctrl, RW>

Output Control Register

pub const fn sm3sts(self) -> Reg<Smsts, RW>

Status Register

pub const fn sm3inten(self) -> Reg<Sminten, RW>

Interrupt Enable Register

pub const fn sm3dmaen(self) -> Reg<Smdmaen, RW>

DMA Enable Register

pub const fn sm3tctrl(self) -> Reg<Smtctrl, RW>

Output Trigger Control Register

pub const fn sm3dismap0(self) -> Reg<Smdismap0, RW>

Fault Disable Mapping Register 0

pub const fn sm3dtcnt0(self) -> Reg<Smdtcnt0, RW>

Deadtime Count Register 0

pub const fn sm3dtcnt1(self) -> Reg<Smdtcnt1, RW>

Deadtime Count Register 1

pub const fn sm3captctrlx(self) -> Reg<Smcaptctrlx, RW>

Capture Control X Register

pub const fn sm3captcompx(self) -> Reg<Smcaptcompx, RW>

Capture Compare X Register

pub const fn sm3cval0(self) -> Reg<Smcval0, R>

Capture Value 0 Register

pub const fn sm3cval0cyc(self) -> Reg<Smcval0cyc, R>

Capture Value 0 Cycle Register

pub const fn sm3cval1(self) -> Reg<Smcval1, R>

Capture Value 1 Register

pub const fn sm3cval1cyc(self) -> Reg<Smcval1cyc, R>

Capture Value 1 Cycle Register

pub const fn sm3phasedly(self) -> Reg<Smphasedly, RW>

Phase Delay Register

pub const fn sm3captfiltx(self) -> Reg<Smcaptfiltx, RW>

Capture PWM_X Input Filter Register

pub const fn outen(self) -> Reg<Outen, RW>

Output Enable Register

pub const fn mask(self) -> Reg<Mask, RW>

Mask Register

pub const fn swcout(self) -> Reg<Swcout, RW>

Software Controlled Output Register

pub const fn dtsrcsel(self) -> Reg<Dtsrcsel, RW>

PWM Source Select Register

pub const fn mctrl(self) -> Reg<Mctrl, RW>

Master Control Register

pub const fn mctrl2(self) -> Reg<Mctrl2, RW>

Master Control 2 Register

pub const fn fctrl0(self) -> Reg<Fctrl0, RW>

Fault Control Register

pub const fn fsts0(self) -> Reg<Fsts0, RW>

Fault Status Register

pub const fn ffilt0(self) -> Reg<Ffilt0, RW>

Fault Filter Register

pub const fn ftst0(self) -> Reg<Ftst0, RW>

Fault Test Register

pub const fn fctrl20(self) -> Reg<Fctrl20, RW>

Fault Control 2 Register

Trait Implementations

impl Clone for Flexpwm

fn clone(&self) -> Flexpwm

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Flexpwm

fn eq(&self, other: &Flexpwm) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Flexpwm

impl Eq for Flexpwm

impl Send for Flexpwm

impl StructuralPartialEq for Flexpwm

impl Sync for Flexpwm