#[repr(u8)]pub enum SmartDmaTrigInp {
Show 128 variants
_RESERVED_0 = 0,
Val1 = 1,
Val2 = 2,
Val3 = 3,
Val4 = 4,
Val5 = 5,
Val6 = 6,
Val7 = 7,
Val8 = 8,
Val9 = 9,
Val10 = 10,
Val11 = 11,
Val12 = 12,
Val13 = 13,
Val14 = 14,
Val15 = 15,
Val16 = 16,
Val17 = 17,
Val18 = 18,
Val19 = 19,
Val20 = 20,
Val21 = 21,
Val22 = 22,
Val23 = 23,
Val24 = 24,
Val25 = 25,
_RESERVED_1a = 26,
Val27 = 27,
_RESERVED_1c = 28,
Val29 = 29,
Val30 = 30,
Val31 = 31,
Val32 = 32,
Val33 = 33,
Val34 = 34,
Val35 = 35,
Val36 = 36,
Val37 = 37,
Val38 = 38,
Val39 = 39,
Val40 = 40,
_RESERVED_29 = 41,
_RESERVED_2a = 42,
_RESERVED_2b = 43,
_RESERVED_2c = 44,
Val45 = 45,
Val46 = 46,
Val47 = 47,
Val48 = 48,
Val49 = 49,
Val50 = 50,
Val51 = 51,
Val52 = 52,
Val53 = 53,
Val54 = 54,
Val55 = 55,
Val56 = 56,
Val57 = 57,
Val58 = 58,
Val59 = 59,
Val60 = 60,
Val61 = 61,
Val62 = 62,
Val63 = 63,
Val64 = 64,
Val65 = 65,
_RESERVED_42 = 66,
Val67 = 67,
Val68 = 68,
Val69 = 69,
_RESERVED_46 = 70,
_RESERVED_47 = 71,
Val72 = 72,
_RESERVED_49 = 73,
_RESERVED_4a = 74,
Val75 = 75,
_RESERVED_4c = 76,
_RESERVED_4d = 77,
Val78 = 78,
_RESERVED_4f = 79,
Val80 = 80,
Val81 = 81,
Val82 = 82,
Val83 = 83,
Val84 = 84,
Val85 = 85,
Val86 = 86,
Val87 = 87,
Val88 = 88,
_RESERVED_59 = 89,
_RESERVED_5a = 90,
_RESERVED_5b = 91,
_RESERVED_5c = 92,
_RESERVED_5d = 93,
_RESERVED_5e = 94,
_RESERVED_5f = 95,
_RESERVED_60 = 96,
_RESERVED_61 = 97,
_RESERVED_62 = 98,
_RESERVED_63 = 99,
_RESERVED_64 = 100,
_RESERVED_65 = 101,
_RESERVED_66 = 102,
_RESERVED_67 = 103,
_RESERVED_68 = 104,
_RESERVED_69 = 105,
_RESERVED_6a = 106,
_RESERVED_6b = 107,
_RESERVED_6c = 108,
_RESERVED_6d = 109,
_RESERVED_6e = 110,
_RESERVED_6f = 111,
_RESERVED_70 = 112,
_RESERVED_71 = 113,
_RESERVED_72 = 114,
_RESERVED_73 = 115,
_RESERVED_74 = 116,
_RESERVED_75 = 117,
_RESERVED_76 = 118,
_RESERVED_77 = 119,
_RESERVED_78 = 120,
_RESERVED_79 = 121,
_RESERVED_7a = 122,
_RESERVED_7b = 123,
_RESERVED_7c = 124,
_RESERVED_7d = 125,
_RESERVED_7e = 126,
_RESERVED_7f = 127,
}Variants§
_RESERVED_0 = 0
Val1 = 1
GPIO P0_16 input is selected.
Val2 = 2
GPIO P0_17 input is selected.
Val3 = 3
GPIO P1_8 input is selected.
Val4 = 4
GPIO P1_9 input is selected.
Val5 = 5
GPIO P1_10 input is selected.
Val6 = 6
GPIO P1_11 input is selected.
Val7 = 7
GPIO P1_12 input is selected.
Val8 = 8
GPIO P1_13 input is selected.
Val9 = 9
GPIO P2_0 input is selected.
Val10 = 10
GPIO P2_1 input is selected.
Val11 = 11
GPIO P2_2 input is selected.
Val12 = 12
GPIO P2_3 input is selected.
Val13 = 13
GPIO P2_6 input is selected.
Val14 = 14
GPIO P3_8 input is selected.
Val15 = 15
GPIO P3_9 input is selected.
Val16 = 16
GPIO P3_10 input is selected.
Val17 = 17
GPIO P3_11 input is selected.
Val18 = 18
GPIO P3_12 input is seclected.
Val19 = 19
GPIO0 Pin Event Trig input is selected.
Val20 = 20
GPIO1 Pin Event Trig input is selected.
Val21 = 21
GPIO2 Pin Event Trig input is selected.
Val22 = 22
GPIO3 Pin Event Trig input is selected.
Val23 = 23
GPIO4 Pin Event Trig input is selected.
Val24 = 24
ARM_TXEV input is selected.
Val25 = 25
AOI0_OUT0 input is selected.
_RESERVED_1a = 26
Val27 = 27
DMA_IRQ input is selected.
_RESERVED_1c = 28
Val29 = 29
WUU_IRQ input is selected.
Val30 = 30
CTimer0_MAT2 input is selected.
Val31 = 31
CTimer0_MAT3 input is selected.
Val32 = 32
CTimer1_MAT2 input is selected.
Val33 = 33
CTimer1_MAT3 input is selected.
Val34 = 34
CTimer2_MAT2 input is selected.
Val35 = 35
CTimer2_MAT3 input is selected.
Val36 = 36
CTimer3_MAT2 input is selected.
Val37 = 37
CTimer3_MAT3 input is selected.
Val38 = 38
CTimer4_MAT2 input is selected.
Val39 = 39
CTimer4_MAT3 input is selected.
Val40 = 40
OSTIMER_IRQ input is selected.
_RESERVED_29 = 41
_RESERVED_2a = 42
_RESERVED_2b = 43
_RESERVED_2c = 44
Val45 = 45
RTC_Alarm_IRQ input is selected.
Val46 = 46
RTC_1Hz_IRQ input is selected.
Val47 = 47
uTICK_IRQ input is selected.
Val48 = 48
WDT_IRQ input is selected.
Val49 = 49
Wakeup_Timer_IRQ input is selected.
Val50 = 50
CAN0_IRQ input is selected.
Val51 = 51
CAN1_IRQ input is selected.
Val52 = 52
FlexIO0_IRQ input is selected.
Val53 = 53
FlexIO0_Shifer0_DMA_Req input is selected.
Val54 = 54
FlexIO0_Shifer1_DMA_Req input is selected.
Val55 = 55
FlexIO0_Shifer2_DMA_Req input is selected.
Val56 = 56
FlexIO0_Shifer3_DMA_Req input is selected.
Val57 = 57
I3C0_IRQ input is selected.
Val58 = 58
LPI2C0_IRQ input is selected.
Val59 = 59
LPI2C1_IRQ input is selected.
Val60 = 60
LPSPI0_IRQ input is selected.
Val61 = 61
LPSPI1_IRQ input is selected.
Val62 = 62
LPUART0_IRQ input is selected.
Val63 = 63
LPUART1_IRQ input is selected.
Val64 = 64
LPUART2_IRQ input is selected.
Val65 = 65
LPUART3_IRQ input is selected.
_RESERVED_42 = 66
Val67 = 67
USB1 Start of Frame input is selected.
Val68 = 68
ADC0_IRQ input is selected.
Val69 = 69
ADC1_IRQ input is selected.
_RESERVED_46 = 70
_RESERVED_47 = 71
Val72 = 72
CMP0_IRQ input is selected.
_RESERVED_49 = 73
_RESERVED_4a = 74
Val75 = 75
CMP0_OUT input is selected.
_RESERVED_4c = 76
_RESERVED_4d = 77
Val78 = 78
DAC0_IRQ input is selected.
_RESERVED_4f = 79
Val80 = 80
DMA1_IRQ input is selected.
Val81 = 81
DAC1_IRQ input is selected.
Val82 = 82
TSI0_End_of_Scan_IRQ input is selected.
Val83 = 83
TSI0_Out_of_Range_IRQ input is selected.
Val84 = 84
ENET QOS IRQ input is selected.
Val85 = 85
10BASE_T1S IRQ input is selected.
Val86 = 86
ERM Interrupt input is selected.
Val87 = 87
TMPR_OUT0 input is selected.
Val88 = 88
TMPR_OUT1 input is selected.
_RESERVED_59 = 89
_RESERVED_5a = 90
_RESERVED_5b = 91
_RESERVED_5c = 92
_RESERVED_5d = 93
_RESERVED_5e = 94
_RESERVED_5f = 95
_RESERVED_60 = 96
_RESERVED_61 = 97
_RESERVED_62 = 98
_RESERVED_63 = 99
_RESERVED_64 = 100
_RESERVED_65 = 101
_RESERVED_66 = 102
_RESERVED_67 = 103
_RESERVED_68 = 104
_RESERVED_69 = 105
_RESERVED_6a = 106
_RESERVED_6b = 107
_RESERVED_6c = 108
_RESERVED_6d = 109
_RESERVED_6e = 110
_RESERVED_6f = 111
_RESERVED_70 = 112
_RESERVED_71 = 113
_RESERVED_72 = 114
_RESERVED_73 = 115
_RESERVED_74 = 116
_RESERVED_75 = 117
_RESERVED_76 = 118
_RESERVED_77 = 119
_RESERVED_78 = 120
_RESERVED_79 = 121
_RESERVED_7a = 122
_RESERVED_7b = 123
_RESERVED_7c = 124
_RESERVED_7d = 125
_RESERVED_7e = 126
_RESERVED_7f = 127
Implementations§
Trait Implementations§
Source§impl Clone for SmartDmaTrigInp
impl Clone for SmartDmaTrigInp
Source§fn clone(&self) -> SmartDmaTrigInp
fn clone(&self) -> SmartDmaTrigInp
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more