Struct Inputmux 

pub struct Inputmux { /* private fields */ }

INPUTMUX

Implementations

impl Inputmux

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn ctimer0cap(self, n: usize) -> Reg<Ctimer0cap, RW>

Capture select register for CTIMER inputs

pub const fn timer0trig(self) -> Reg<Timer0trig, RW>

Trigger register for TIMER0

pub const fn ctimer1cap(self, n: usize) -> Reg<Ctimer1cap, RW>

Capture select register for CTIMER inputs

pub const fn timer1trig(self) -> Reg<Timer1trig, RW>

Trigger register for TIMER1

pub const fn ctimer2cap(self, n: usize) -> Reg<Ctimer2cap, RW>

Capture select register for CTIMER inputs

pub const fn timer2trig(self) -> Reg<Timer2trig, RW>

Trigger register for TIMER2 inputs

pub const fn smart_dma_trig(self, n: usize) -> Reg<SmartDmaTrig, RW>

SmartDMA Trigger Input Connections

pub const fn freqmeas_ref(self) -> Reg<FreqmeasRef, RW>

Selection for frequency measurement reference clock

pub const fn freqmeas_tar(self) -> Reg<FreqmeasTar, RW>

Selection for frequency measurement reference clock

pub const fn ctimer3cap(self, n: usize) -> Reg<Ctimer3cap, RW>

Capture select register for CTIMER inputs

pub const fn timer3trig(self) -> Reg<Timer3trig, RW>

Trigger register for TIMER3

pub const fn ctimer4cap(self, n: usize) -> Reg<Ctimer4cap, RW>

Capture select register for CTIMER inputs

pub const fn timer4trig(self) -> Reg<Timer4trig, RW>

Trigger register for TIMER4

pub const fn aoi1_input(self, n: usize) -> Reg<AoiInput, RW>

AOI1 trigger input connections 0

pub const fn cmp0_trig(self) -> Reg<CmpTrig, RW>

CMP0 input connections

pub const fn adc0_trig(self, n: usize) -> Reg<AdcTrig, RW>

ADC Trigger input connections

pub const fn adc2_trig(self, n: usize) -> Reg<AdcTrig, RW>

ADC Trigger input connections

pub const fn adc1_trig(self, n: usize) -> Reg<AdcTrig, RW>

ADC Trigger input connections

pub const fn adc3_trig(self, n: usize) -> Reg<AdcTrig, RW>

ADC Trigger input connections

pub const fn dac0_trig(self) -> Reg<DacTrig, RW>

DAC0 Trigger input connections.

pub const fn qdc0_trig(self) -> Reg<QdcTrig, RW>

QDC0 Trigger Input Connections

pub const fn qdc0_home(self) -> Reg<Qdc0Home, RW>

QDC0 Trigger Input Connections

pub const fn qdc0_index(self) -> Reg<Qdc0Index, RW>

QDC0 Trigger Input Connections

pub const fn qdc0_phaseb(self) -> Reg<Qdc0Phaseb, RW>

QDC0 Trigger Input Connections

pub const fn qdc0_phasea(self) -> Reg<Qdc0Phasea, RW>

QDC0 Trigger Input Connections

pub const fn qdc0_icap1(self) -> Reg<Qdc0Icap1, RW>

QDC0 Trigger Input Connections

pub const fn qdc0_icap2(self) -> Reg<Qdc0Icap2, RW>

QDC0 Trigger Input Connections

pub const fn qdc0_icap3(self) -> Reg<Qdc0Icap3, RW>

QDC0 Trigger Input Connections

pub const fn qdc1_trig(self) -> Reg<QdcTrig, RW>

QDC1 Trigger Input Connections

pub const fn qdc1_home(self) -> Reg<Qdc1Home, RW>

QDC1 Trigger Input Connections

pub const fn qdc1_index(self) -> Reg<Qdc1Index, RW>

QDC1 Trigger Input Connections

pub const fn qdc1_phaseb(self) -> Reg<Qdc1Phaseb, RW>

QDC1 Trigger Input Connections

pub const fn qdc1_phasea(self) -> Reg<Qdc1Phasea, RW>

QDC1 Trigger Input Connections

pub const fn qdc1_icap1(self) -> Reg<Qdc1Icap1, RW>

QDC1 Trigger Input Connections

pub const fn qdc1_icap2(self) -> Reg<Qdc1Icap2, RW>

QDC1 Trigger Input Connections

pub const fn qdc1_icap3(self) -> Reg<Qdc1Icap3, RW>

QDC1 Trigger Input Connections

pub const fn flex_pwm0_sm0_exta0(self) -> Reg<FlexPwm, RW>

PWM0 input trigger connections

pub const fn flex_pwm0_sm0_extsync(self) -> Reg<FlexPwm, RW>

PWM0 input trigger connections

pub const fn flex_pwm0_sm1_exta(self) -> Reg<FlexPwm, RW>

PWM0 input trigger connections

pub const fn flex_pwm0_sm1_extsync(self) -> Reg<FlexPwm, RW>

PWM0 input trigger connections

pub const fn flex_pwm0_sm2_exta(self) -> Reg<FlexPwm, RW>

PWM0 input trigger connections

pub const fn flex_pwm0_sm2_extsync(self) -> Reg<FlexPwm, RW>

PWM0 input trigger connections

pub const fn flex_pwm0_sm3_exta0(self) -> Reg<FlexPwm, RW>

PWM0 input trigger connections

pub const fn flex_pwm0_sm3_extsync(self) -> Reg<FlexPwm, RW>

PWM0 input trigger connections

pub const fn flex_pwm0_fault(self, n: usize) -> Reg<FlexPwm, RW>

PWM0 Fault Input Trigger Connections

pub const fn flex_pwm0_force(self) -> Reg<FlexPwm, RW>

PWM0 input trigger connections

pub const fn flex_pwm1_sm0_exta0(self) -> Reg<FlexPwm, RW>

PWM1 input trigger connections

pub const fn flex_pwm1_sm0_extsync(self) -> Reg<FlexPwm, RW>

PWM1 input trigger connections

pub const fn flex_pwm1_sm1_exta(self) -> Reg<FlexPwm, RW>

PWM1 input trigger connections

pub const fn flex_pwm1_sm1_extsync(self) -> Reg<FlexPwm, RW>

PWM1 input trigger connections

pub const fn flex_pwm1_sm2_exta(self) -> Reg<FlexPwm, RW>

PWM1 input trigger connections

pub const fn flex_pwm1_sm2_extsync(self) -> Reg<FlexPwm, RW>

PWM1 input trigger connections

pub const fn flex_pwm1_sm3_exta0(self) -> Reg<FlexPwm, RW>

PWM1 input trigger connections

pub const fn flex_pwm1_sm3_extsync(self) -> Reg<FlexPwm, RW>

PWM1 input trigger connections

pub const fn flex_pwm1_fault(self, n: usize) -> Reg<FlexPwm, RW>

PWM1 Fault Input Trigger Connections

pub const fn flex_pwm1_force(self) -> Reg<FlexPwm, RW>

PWM1 input trigger connections

pub const fn pwm0_ext_clk(self) -> Reg<Pwm0ExtClk, RW>

PWM0 external clock trigger

pub const fn pwm1_ext_clk(self) -> Reg<Pwm1ExtClk, RW>

PWM1 external clock trigger

pub const fn aoi0_input(self, n: usize) -> Reg<AoiInput, RW>

AOI0 trigger input connections 0

pub const fn usbfs_trig(self) -> Reg<UsbfsTrig, RW>

USB-FS trigger input connections

pub const fn ext_trig(self, n: usize) -> Reg<ExtTrig, RW>

EXT trigger connections

pub const fn cmp1_trig(self) -> Reg<CmpTrig, RW>

CMP1 input connections

pub const fn cmp2_trig(self) -> Reg<CmpTrig, RW>

CMP2 input connections

pub const fn lpi2c2_trig(self) -> Reg<Lpi2cTrig, RW>

LPI2C2 trigger input connections

pub const fn lpi2c3_trig(self) -> Reg<Lpi2cTrig, RW>

LPI2C3 trigger input connections

pub const fn lpi2c0_trig(self) -> Reg<Lpi2cTrig, RW>

LPI2C0 trigger input connections

pub const fn lpi2c1_trig(self) -> Reg<Lpi2cTrig, RW>

LPI2C1 trigger input connections

pub const fn lpspi0_trig(self) -> Reg<LpspiTrig, RW>

LPSPI0 trigger input connections

pub const fn lpspi1_trig(self) -> Reg<LpspiTrig, RW>

LPSPI1 trigger input connections

pub const fn lpuart(self, n: usize) -> Reg<Lpuart, RW>

LPUART0 trigger input connections

pub const fn flexio_trig(self, n: usize) -> Reg<FlexioTrig, RW>

FlexIO Trigger Input Connections

pub const fn trigfil_prsc(self) -> Reg<TrigfilPrsc, RW>

Trigger filter prescaller

pub const fn trigfil_stat0(self) -> Reg<TrigfilStat, R>

Trigger filter stat

pub const fn trigfil(self, n: usize) -> Reg<Trigfil, RW>

TRIGFIL control

Trait Implementations

impl Clone for Inputmux

fn clone(&self) -> Inputmux

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Inputmux

fn eq(&self, other: &Inputmux) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Inputmux

impl Eq for Inputmux

impl Send for Inputmux

impl StructuralPartialEq for Inputmux

impl Sync for Inputmux