Module usbhs 

Peripheral access API (generated using chiptool v0.1.0 (e890244 2026-11-05))

Structs

Asynclistaddr

Next Asynchronous Address. F70RM 44.6.1.25 (text line 114575). Host-mode interpretation of 0x158; ENDPTLISTADDR is the device-mode alias. ASYBASE encodes address bits 31:5.

Burstsize

Programmable Burst Size. F70RM 44.6.1.27 (text line 114696).

Caplength

Capability Registers Length. F70RM 44.6.1.13 (text line 112922).

Configflag

Configure Flag. F70RM 44.6.1.31 (text line 115049). Read-only in the register map/diagram; generic prose about setting CF does not establish a writable implementation on this chip.

Dccparams

Device Controller Capability Parameters. F70RM 44.6.1.18 (text line 113282). DEN is a raw endpoint count (valid 0..15 in the field prose); reset count is 8. The abbreviated encoding table listing 0 and 1 is not an exhaustive count enum.

Dciversion

Device Controller Interface Version. F70RM 44.6.1.17 (text line 113238).

Deviceaddr

Device Address. F70RM 44.6.1.23 (text line 114438). Device-mode interpretation of 0x154; PERIODICLISTBASE is the host-mode alias. USBADRA defers the address update until the status phase completes.

Endptcomplete

Endpoint Complete. F70RM 44.6.1.39 (text line 116329). Device-mode RX/TX completion masks for endpoints 0..7, W1C (register diagram). Read the associated queue to determine transfer status; acknowledge only the intended mask.

Endptctrl

Endpoint Control 1. F70RM 44.6.1.41 (text line 116553). Device endpoints 1..7 (array index 0 is endpoint 1). RXT/TXT: 0 control, 1 isochronous, 2 bulk, 3 interrupt. RXR/TXR are write-only data-toggle-reset commands. RXD/TXD must remain 0. RXI/TXI are test controls and must remain 0 for normal operation. Configure before enabling. RM setup-stall prose says both becomes 1 and hardware writes 0; this conflict is not resolved here.

Endptctrl0

Endpoint Control 0. F70RM 44.6.1.40 (text line 116409). Device endpoint 0 only, permanently enabled as control endpoint; RXT, TXT, RXE, TXE are read-only in the diagram. Stall bits clear on setup reception and remain hardware-cleared until setup status is acknowledged (up to 50 clocks delay).

Endptflush

Endpoint Flush. F70RM 44.6.1.37 (text line 116154). Device-mode RX/TX command masks for endpoints 0..7. Writing 1 flushes; current packets complete and hardware clears bits after the operation succeeds.

Endptlistaddr

Endpoint List Address. F70RM 44.6.1.26 (text line 114635). Device-mode interpretation of 0x158; ASYNCLISTADDR is the host-mode alias. EPBASE encodes address bits 31:11. This controller implements eight endpoint pairs, not the generic 32-queue-head maximum.

Endptnak

Endpoint NAK. F70RM 44.6.1.29 (text line 114882). Device-mode RX/TX bit masks for endpoints 0..7, W1C. Write only the intended acknowledgement mask; no two-state enum.

Endptnaken

Endpoint NAK Enable. F70RM 44.6.1.30 (text line 114980). Device-mode RX/TX enable masks for endpoints 0..7.

Endptprime

Endpoint Prime. F70RM 44.6.1.36 (text line 116055). Device-mode RX/TX command masks for endpoints 0..7. Writing 1 requests priming; hardware clears a bit when primed and may temporarily set it while repriming. Not an ordinary stored enable.

Endptsetupstat

Endpoint Setup Status. F70RM 44.6.1.35 (text line 115973). Device-mode W1C endpoint setup status mask. The manual explicitly draws 15:0; only endpoints 0..7 are implemented (valid endpoint mask 0x00ff). Bits 15:8 do not imply additional endpoints.

Endptstat

Endpoint Status. F70RM 44.6.1.38 (text line 116226). Read-only device-mode RX/TX readiness masks for endpoints 0..7. May transiently clear during hardware repriming.

Frindex

USB Frame Index. F70RM 44.6.1.22 (text line 114351). Raw numeric frame/microframe counter. In Host mode it updates every 125 microseconds; bits n:3 index the periodic frame list, with n selected by USBCMD frame-list size. Bits 13:3 contain the frame number and bits 2:0 the microframe. Only 32-bit writes are defined, and Host-mode writes require the Halted state (USBSTS.HCH=1, USBCMD.RS=0); writes also affect the SOF value. In Device mode the register is read-only and the received SOF updates the frame/microframe counter. The table in RM 44.6.1.22 refers to USBCMD frame-list-size encodings, not legal FRINDEX counter values.

Gptimer0ctrl

General Purpose Timer 0 Controller. F70RM 44.6.1.9 (text line 112604). GPTCNT is read-only; GPTRST is a write-only load command. Avoid read-modify-write on command bits.

Gptimer0ld

General Purpose Timer 0 Load. F70RM 44.6.1.8 (text line 112541).

Gptimer1ctrl

General Purpose Timer 1 Controller. F70RM 44.6.1.11 (text line 112748). GPTCNT is read-only; GPTRST is a write-only load command. RM .10-.11 refer to timer 0 in timer 1 prose; those cross-references conflict with the timer 1 register names and are not resolved here.

Gptimer1ld

General Purpose Timer 1 Load. F70RM 44.6.1.10 (text line 112693).

Hccparams

Host Controller Capability Parameters. F70RM 44.6.1.16 (text line 113129).

Hciversion

Host Controller Interface Version. F70RM 44.6.1.14 (text line 112966). Source conflict: map/diagram reset is 0x0100, but prose calls the default 0x10 for EHCI revision 1.0. Retain the map reset and raw version value.

Hcsparams

Host Controller Structural Parameters. F70RM 44.6.1.15 (text line 113003).

Hwdevice

Device Hardware Parameters. F70RM 44.6.1.5 (text line 112347).

Hwgeneral

Hardware General. F70RM 44.6.1.3 (text line 112178).

Hwhost

Host Hardware Parameters. F70RM 44.6.1.4 (text line 112284).

Hwrxbuf

RX Buffer Hardware Parameters. F70RM 44.6.1.7 (text line 112478).

Hwtxbuf

TX Buffer Hardware Parameters. F70RM 44.6.1.6 (text line 112408). Source conflict: map/diagram reset 0x80050808 gives TXCHANADD=5, but field prose says 8 and 256x4 bytes per TX endpoint. Retain the map reset and raw size exponent without asserting a corrected buffer capacity. Eight TX endpoints are explicitly documented.

Id

Identification. F70RM 44.6.1.2 (text line 112108).

NcClkRecoverCtrl

USB Clock Recovery Control. F70RM 44.5.1.8 (text line 111672). 8-bit storage/access. Clock recovery is only for crystal-less FS Device mode, never Host mode or HS Device mode.

NcClkRecoverIntEn

Clock Recovery Combined Interrupt Enable. F70RM 44.5.1.10 (text line 111847).

NcClkRecoverIntStatus

Clock Recovery Separated Interrupt Status. F70RM 44.5.1.11 (text line 111909). 8-bit storage/access. OVF_ERROR is W1C; writing 0 has no effect.

NcClkRecoverIrcEn

FIRC Oscillator Enable. F70RM 44.5.1.9 (text line 111776). 8-bit storage/access. IRC_EN and CLOCK_RECOVER_EN must both be set for crystal-less FS Device mode. Reserved reset bit 0 is retained, not exposed as an enable.

NcCtrl1

USB Control 1. F70RM 44.5.1.2 (text line 110945). Preserve reserved bits. WIR is read-only and clears by disabling WIE, not W1C. WKUP_DPDM_EN is Device-mode only (disable only while VBUS invalid); REMOTE_WAKEUP_EN is Host-mode only.

NcCtrl2

USB Control 2. F70RM 44.5.1.3 (text line 111143). Preserve reserved bits. UTMI_CLK_VLD is W1C (write 0 has no effect). VBUS_SOURCE_SEL: 0 vbus_valid; 1,2,3 sess_valid; all four encodings are legal.

NcHsicDllCfg4

HSIC DLL Configuration 4. F70RM 44.5.1.4 (text line 111226). Preserve reserved bits, including reset bit 6. FS_ISO_B2B_FIXEN is only for a directly connected FS device and must not be set when the FS device is behind a hub.

NcLpmCsr0

USB LPM Control and Status 0. F70RM 44.5.1.5 (text line 111294).

NcLpmCsr1

USB LPM Control and Status 1. F70RM 44.5.1.6 (text line 111415).

NcLpmCsr2

USB LPM Control and Status 2. F70RM 44.5.1.7 (text line 111573). LPM_HST_SEND is a self-clearing command, allowed only in L0. Response status is read-only: 0 invalid, 1 ACK, 2 NYET, 3 STALL, 4 timeout, 5 ERR, 6..7 reserved.

Otgsc

On-The-Go Status and Control. F70RM 44.6.1.33 (text line 115583). Mixed controls/read-only inputs and W1C interrupt status bits 22:16. Known reset mask 0xffdfc1ff, known value 0x20; bits 21 and 13:9 are unknown. Generated reset_value is a construction default only. HADP is a write command; do not replay commands or W1C flags with an unmasked read-modify-write.

Periodiclistbase

Frame List Base Address. F70RM 44.6.1.24 (text line 114514). Host-mode interpretation of 0x154; DEVICEADDR is the device-mode alias. BASEADR encodes address bits 31:12, not an unshifted pointer.

Portsc1

Port Status and Control. F70RM 44.6.1.32 (text line 115111). Mixed control/read-only status and W1C CSC, PEC, OCC. Unmasked read-modify-write can acknowledge pending changes. PR and SUSP are read-only in Device mode; PR/FPR self-clear after signaling. PE is always 1 in Device mode; in Host mode software can disable but cannot enable it by writing 1. This chip uses the 16-bit UTMI interface (HWGENERAL reset 0x1015); generic alternative PHY encodings do not establish chip support.

Sbuscfg

System Bus Configuration. F70RM 44.6.1.12 (text line 112843).

Txfilltuning

TX FIFO Fill Tuning. F70RM 44.6.1.28 (text line 114761). Writing this register clears TXSCHHEALTH, regardless of the written counter value. TXFIFOTHRES minimum is 2; ignored when USBMODE.SDIS=1.

Usbcmd

USB Command. F70RM 44.6.1.19 (text line 113363). RST and IAA are self-clearing commands. Host reset requires HCH=1. Device reset requires flushed endpoints and RS=0. FS_2:FS_1 jointly select 1024,512,256,128,64,32,16,8 frame-list elements. ITC legal values are 0,1,2,4,8,16,32,64. RM ASP/ASPE prose defaults (3/1) conflict with the register-map/diagram reset 0x00080000; the diagram is retained without guessing a mode-specific alternative.

Usbhs

MCXA5 USB HS controller. One port, eight IN/OUT endpoint pairs. Host/device aliases share addresses; select the interpretation for USBMODE.CM.

Usbintr

Interrupt Enable. F70RM 44.6.1.21 (text line 114100).

Usbmode

USB Device Mode. F70RM 44.6.1.34 (text line 115822). CM is programmed once after reset on this host/device controller; changing mode requires controller reset. CM: 0 idle, 1 reserved, 2 device, 3 host. SLOM=0 enables setup lockouts; SLOM=1 disables them and requires the setup-data tripwire.

Usbnc

USB noncore window, relative to controller +0x200. Preserve reserved values on writes.

Usbsts

USB Status. F70RM 44.6.1.20 (text line 113592). Mixed read-only status and W1C interrupt flags; never acknowledge via an unmasked read-modify-write. Known reset mask 0xffffff7f, known value 0; SRI reset is unknown. Generated reset_value is a construction default, not a fully known hardware reset.