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Module tdet

Module tdet 

Source
Expand description

Peripheral access API (generated using chiptool v0.1.0 (e890244 2026-11-05))

Structs§

Cr
Control
Ier
Interrupt Enable
Lr
One-way lock bits until VBAT POR or TDET software reset. Locked writes are ignored without bus error. Locking CR disables software reset; locking LR itself prevents further lock changes.
Pgfr
Pin Glitch Filter
Ppr
Pin Polarity
Rac
Read Access Control
Sr
Status
Tdet
Digital tamper. Word writes only. TSR writes create tamper events. SR table defaults contradict the reset-condition prose and are not confirmed post-reset observations. No device operations are performed by this model.
Ter
Tamper Enable
Tsr
Tamper Seconds
Wac
Write Access Control

Enums§

CrDen
CrDistam
CrSwr
CrTfsr
CrUm
IerDtie
IerTiie0
IerTiie6
IerTiie10
IerTpie0
IerTpie1
IerTpie2
IerTpie3
IerTpie4
IerTpie5
IerTpie6
IerTpie7
LrCrl
LrGfl0
LrGfl1
LrGfl2
LrGfl3
LrGfl4
LrGfl5
LrGfl6
LrGfl7
LrIel
LrLrl
LrPpl
LrSrl
LrTel
LrTsl
PgfrGfe
PgfrGfp
PgfrTpe
PgfrTps
PgfrTpsf
PgfrTpsw
PprTpid0
PprTpid1
PprTpid2
PprTpid3
PprTpid4
PprTpid5
PprTpid6
PprTpid7
PprTpp0
PprTpp1
PprTpp2
PprTpp3
PprTpp4
PprTpp5
PprTpp6
PprTpp7
RacCrr
RacGfr0
RacGfr1
RacGfr2
RacGfr3
RacGfr4
RacGfr5
RacGfr6
RacGfr7
RacIer
RacLrr
RacPpr
RacSrr
RacTer
RacTsrr
SrDtf
SrTaf
SrTif0
SrTif6
SrTif10
SrTpf0
SrTpf1
SrTpf2
SrTpf3
SrTpf4
SrTpf5
SrTpf6
SrTpf7
TerTie0
TerTie6
TerTie10
TerTpe0
TerTpe1
TerTpe2
TerTpe3
TerTpe4
TerTpe5
TerTpe6
TerTpe7
WacCrw
WacGfw0
WacGfw1
WacGfw2
WacGfw3
WacGfw4
WacGfw5
WacGfw6
WacGfw7
WacIew
WacLrw
WacPpw
WacSrw
WacTew
WacTsrw