Module seccon 

Peripheral access API (generated using chiptool v0.1.0 (e890244 2026-11-05))

Structs

CfpaLcState

CFPA State Register Hardware reset contains unknown bits. Known-zero mask0x00000000; all other reset bits are unknown. Generated zero default is only a construction value, NOT a complete hardware reset value.

Cpu0stckcal

Secure CPU0 System Tick Calibration Hardware reset contains unknown bits. Known-zero mask0x03FFFFFF; all other reset bits are unknown. Generated zero default is only a construction value, NOT a complete hardware reset value.

DebugAuthBeacon

Debug Authentication BEACON Application-side read-only after ROM handoff; reset on PoR only.

DebugFeatures

Cortex Debug Features Control Hardware reset contains unknown bits. Known-zero mask0x00000000; all other reset bits are unknown. Generated zero default is only a construction value, NOT a complete hardware reset value. Reset on PoR only.

DebugFeaturesDp

Cortex Debug Features Control (Duplicate) Hardware reset contains unknown bits. Known-zero mask0x00000000; all other reset bits are unknown. Generated zero default is only a construction value, NOT a complete hardware reset value. Protected by GLIKEY index1 with GLIKEY reset function, distinct from DEBUG_FEATURES.

DebugLockEn

Control Write Access to Security

ElsOtpLcState

Life Cycle State Register Hardware reset contains unknown bits. Known-zero mask0xFFFFFF00; all other reset bits are unknown. Generated zero default is only a construction value, NOT a complete hardware reset value.

ElsOtpLcStateDp

Life Cycle State Register (Duplicate) Hardware reset contains unknown bits. Known-zero mask0xFFFFFF00; all other reset bits are unknown. Generated zero default is only a construction value, NOT a complete hardware reset value.

Gdet0Ctrl

GDET0 Control Register

Msfcfg

MSF Configuration

RamXen

RAM XEN Control

RamXenDp

RAM XEN Control (Duplicate) Protected by GLIKEY index2; no LOCK field.

Seccon

Core/application-side security-controller register view. Source model only: no provisioning, authentication, lock, erase or lifecycle operation is performed. Unknown reset bits remain unknown; generated defaults are construction values, not observed device state.

SwdAccessCpu0

CPU0 Software Debug Access

Enums

Cpu0stckcalNoref

Cpu0stckcalSkew

DebugFeature

Gdet0CtrlEventClrFlag

Gdet0CtrlGdetErrClr

Gdet0CtrlGdetEvtcntClr

Gdet0CtrlGdetIsoSw

Gdet0CtrlNegSync

Gdet0CtrlPosSync

MsfcfgCgOverride

MsfcfgIfrBlock0EraseDis0

MsfcfgIfrBlock0EraseDis1

MsfcfgIfrBlock0EraseDis2

MsfcfgIfrBlock0EraseDis3

MsfcfgIfrBlock1EraseDis0

MsfcfgIfrBlock1EraseDis1

MsfcfgIfrBlock1EraseDis2

MsfcfgIfrBlock1EraseDis3

MsfcfgMassEraseDis

RamXenLock

RamXenRama0Xen

RamXenRama1Xen

RamXenRambXen

RamXenRamx0Xen