Struct Mrcc 

pub struct Mrcc { /* private fields */ }

MRCC

Implementations

impl Mrcc

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn mrcc_glb_rst0(self) -> Reg<MrccGlbRst0, RW>

Peripheral Reset Control 0

pub const fn mrcc_glb_rst0_set(self) -> Reg<GlbRstSet, W>

Peripheral Reset Control Set 0

pub const fn mrcc_glb_rst0_clr(self) -> Reg<GlbRstClr, W>

Peripheral Reset Control Clear 0

pub const fn mrcc_glb_rst1(self) -> Reg<MrccGlbRst1, RW>

Peripheral Reset Control 1

pub const fn mrcc_glb_rst1_set(self) -> Reg<GlbRstSet, W>

Peripheral Reset Control Set 1

pub const fn mrcc_glb_rst1_clr(self) -> Reg<GlbRstClr, W>

Peripheral Reset Control Clear 1

pub const fn mrcc_glb_rst2(self) -> Reg<MrccGlbRst2, RW>

Peripheral Reset Control 2

pub const fn mrcc_glb_rst2_set(self) -> Reg<GlbRstSet, W>

Peripheral Reset Control Set 2

pub const fn mrcc_glb_rst2_clr(self) -> Reg<GlbRstClr, W>

Peripheral Reset Control Clear 2

pub const fn mrcc_glb_rst3(self) -> Reg<MrccGlbRst3, RW>

Peripheral Reset Control 3

pub const fn mrcc_glb_rst3_set(self) -> Reg<GlbRstSet, W>

Peripheral Reset Control Set 3

pub const fn mrcc_glb_rst3_clr(self) -> Reg<GlbRstClr, W>

Peripheral Reset Control Clear 3

pub const fn mrcc_glb_rst4(self) -> Reg<MrccGlbRst4, RW>

Peripheral Reset Control 4

pub const fn mrcc_glb_rst4_set(self) -> Reg<GlbRstSet, W>

Peripheral Reset Control Set 4

pub const fn mrcc_glb_rst4_clr(self) -> Reg<GlbRstClr, W>

Peripheral Reset Control Clear 4

pub const fn mrcc_glb_cc0(self) -> Reg<MrccGlbCc0, RW>

AHB Clock Control 0

pub const fn mrcc_glb_cc0_set(self) -> Reg<GlbCcSet, W>

AHB Clock Control Set 0

pub const fn mrcc_glb_cc0_clr(self) -> Reg<GlbCcClr, W>

AHB Clock Control Clear 0

pub const fn mrcc_glb_cc1(self) -> Reg<MrccGlbCc1, RW>

AHB Clock Control 1

pub const fn mrcc_glb_cc1_set(self) -> Reg<GlbCcSet, W>

AHB Clock Control Set 1

pub const fn mrcc_glb_cc1_clr(self) -> Reg<GlbCcClr, W>

AHB Clock Control Clear 1

pub const fn mrcc_glb_cc2(self) -> Reg<MrccGlbCc2, RW>

AHB Clock Control 2

pub const fn mrcc_glb_cc2_set(self) -> Reg<GlbCcSet, W>

AHB Clock Control Set 2

pub const fn mrcc_glb_cc2_clr(self) -> Reg<GlbCcClr, W>

AHB Clock Control Clear 2

pub const fn mrcc_glb_cc3(self) -> Reg<MrccGlbCc3, RW>

AHB Clock Control 3

pub const fn mrcc_glb_cc3_set(self) -> Reg<GlbCcSet, W>

AHB Clock Control Set 3

pub const fn mrcc_glb_cc3_clr(self) -> Reg<GlbCcClr, W>

AHB Clock Control Clear 3

pub const fn mrcc_glb_cc4(self) -> Reg<MrccGlbCc4, RW>

AHB Clock Control 4

pub const fn mrcc_glb_cc4_set(self) -> Reg<GlbCcSet, W>

AHB Clock Control Set 4

pub const fn mrcc_glb_cc4_clr(self) -> Reg<GlbCcClr, W>

AHB Clock Control Clear 4

pub const fn mrcc_glb_acc0(self) -> Reg<MrccGlbAcc0, RW>

Control Automatic Clock Gating 0

pub const fn mrcc_glb_acc1(self) -> Reg<MrccGlbAcc1, RW>

Control Automatic Clock Gating 1

pub const fn mrcc_glb_acc2(self) -> Reg<MrccGlbAcc2, RW>

Control Automatic Clock Gating 2

pub const fn mrcc_glb_acc3(self) -> Reg<MrccGlbAcc3, RW>

Control Automatic Clock Gating 3

pub const fn mrcc_glb_acc4(self) -> Reg<MrccGlbAcc4, RW>

Control Automatic Clock Gating 4

pub const fn mrcc_glb_pr0(self) -> Reg<MrccGlbPr0, RW>

Peripheral Enable Configuration 0. Reset on POR only.

pub const fn mrcc_glb_pr1(self) -> Reg<MrccGlbPr1, RW>

Peripheral Enable Configuration 1. Reset on POR only.

pub const fn mrcc_glb_pr2(self) -> Reg<MrccGlbPr2, RW>

Peripheral Enable Configuration 2. Reset on POR only.

pub const fn mrcc_glb_pr3(self) -> Reg<MrccGlbPr3, RW>

Peripheral Enable Configuration 3. Reset on POR only.

pub const fn mrcc_glb_pr4(self) -> Reg<MrccGlbPr4, RW>

Peripheral Enable Configuration 4. Reset on POR only.

pub const fn mrcc_i3c0_fclk_clksel(self) -> Reg<I3cFclkClksel, RW>

I3C0_FCLK clock selection control

pub const fn mrcc_i3c0_fclk_clkdiv(self) -> Reg<I3cFclkClkdiv, RW>

I3C0_FCLK clock divider control

pub const fn mrcc_i3c1_fclk_clksel(self) -> Reg<I3cFclkClksel, RW>

I3C1_FCLK clock selection control

pub const fn mrcc_i3c1_fclk_clkdiv(self) -> Reg<I3cFclkClkdiv, RW>

I3C1_FCLK clock divider control

pub const fn mrcc_ctimer0_clksel(self) -> Reg<CtimerClksel, RW>

CTIMER0 clock selection control

pub const fn mrcc_ctimer0_clkdiv(self) -> Reg<CtimerClkdiv, RW>

CTIMER0 clock divider control

pub const fn mrcc_ctimer1_clksel(self) -> Reg<CtimerClksel, RW>

CTIMER1 clock selection control

pub const fn mrcc_ctimer1_clkdiv(self) -> Reg<CtimerClkdiv, RW>

CTIMER1 clock divider control

pub const fn mrcc_ctimer2_clksel(self) -> Reg<CtimerClksel, RW>

CTIMER2 clock selection control

pub const fn mrcc_ctimer2_clkdiv(self) -> Reg<CtimerClkdiv, RW>

CTIMER2 clock divider control

pub const fn mrcc_ctimer3_clksel(self) -> Reg<CtimerClksel, RW>

CTIMER3 clock selection control

pub const fn mrcc_ctimer3_clkdiv(self) -> Reg<CtimerClkdiv, RW>

CTIMER3 clock divider control

pub const fn mrcc_ctimer4_clksel(self) -> Reg<CtimerClksel, RW>

CTIMER4 clock selection control

pub const fn mrcc_ctimer4_clkdiv(self) -> Reg<CtimerClkdiv, RW>

CTIMER4 clock divider control

pub const fn mrcc_wwdt0_clkdiv(self) -> Reg<WwdtClkdiv, RW>

WWDT0 clock divider control

pub const fn mrcc_wwdt1_clksel(self) -> Reg<WwdtClksel, RW>

WWDT1 clock selection control

pub const fn mrcc_wwdt1_clkdiv(self) -> Reg<WwdtClkdiv, RW>

WWDT1 clock divider control

pub const fn mrcc_e1588_clksel(self) -> Reg<E158Clksel, RW>

E1588 clock selection control

pub const fn mrcc_e1588_clkdiv(self) -> Reg<E158Clkdiv, RW>

E1588 clock divider control

pub const fn mrcc_rmii_clksel(self) -> Reg<MrccRmiiClksel, RW>

RMII clock selection control

pub const fn mrcc_rmii_clkdiv(self) -> Reg<MrccRmiiClkdiv, RW>

RMII clock divider control

pub const fn mrcc_espi0_clksel(self) -> Reg<EspiClksel, RW>

ESPI0 clock selection control

pub const fn mrcc_espi0_clkdiv(self) -> Reg<EspiClkdiv, RW>

ESPI0 clock divider control

pub const fn mrcc_flexspi0_clksel(self) -> Reg<FlexspiClksel, RW>

FLEXSPI0 clock selection control

pub const fn mrcc_flexspi0_clkdiv(self) -> Reg<FlexspiClkdiv, RW>

FLEXSPI0 clock divider control

pub const fn mrcc_lpspi2_clksel(self) -> Reg<LpspiClksel, RW>

LPSPI2 clock selection control

pub const fn mrcc_lpspi2_clkdiv(self) -> Reg<LpspiClkdiv, RW>

LPSPI2 clock divider control

pub const fn mrcc_lpspi3_clksel(self) -> Reg<LpspiClksel, RW>

LPSPI3 clock selection control

pub const fn mrcc_lpspi3_clkdiv(self) -> Reg<LpspiClkdiv, RW>

LPSPI3 clock divider control

pub const fn mrcc_lpspi4_clksel(self) -> Reg<LpspiClksel, RW>

LPSPI4 clock selection control

pub const fn mrcc_lpspi4_clkdiv(self) -> Reg<LpspiClkdiv, RW>

LPSPI4 clock divider control

pub const fn mrcc_lpspi5_clksel(self) -> Reg<LpspiClksel, RW>

LPSPI5 clock selection control

pub const fn mrcc_lpspi5_clkdiv(self) -> Reg<LpspiClkdiv, RW>

LPSPI5 clock divider control

pub const fn mrcc_t1s0_clksel(self) -> Reg<T1sClksel, RW>

T1S0 clock selection control

pub const fn mrcc_t1s0_clkdiv(self) -> Reg<T1sClkdiv, RW>

T1S0 clock divider control

pub const fn mrcc_usb1_clksel(self) -> Reg<UsbClksel, RW>

USB1 clock selection control

pub const fn mrcc_usb1_phy_clksel(self) -> Reg<UsbPhyClksel, RW>

USB1_PHY clock selection control

pub const fn mrcc_usb1_phy_clkdiv(self) -> Reg<UsbPhyClkdiv, RW>

USB1_PHY clock divider control

pub const fn mrcc_flexio0_clksel(self) -> Reg<FlexioClksel, RW>

FLEXIO0 clock selection control

pub const fn mrcc_flexio0_clkdiv(self) -> Reg<FlexioClkdiv, RW>

FLEXIO0 clock divider control

pub const fn mrcc_lpi2c0_clksel(self) -> Reg<Lpi2cClksel, RW>

LPI2C0 clock selection control

pub const fn mrcc_lpi2c0_clkdiv(self) -> Reg<Lpi2cClkdiv, RW>

LPI2C0 clock divider control

pub const fn mrcc_lpi2c1_clksel(self) -> Reg<Lpi2cClksel, RW>

LPI2C1 clock selection control

pub const fn mrcc_lpi2c1_clkdiv(self) -> Reg<Lpi2cClkdiv, RW>

LPI2C1 clock divider control

pub const fn mrcc_lpspi0_clksel(self) -> Reg<LpspiClksel, RW>

LPSPI0 clock selection control

pub const fn mrcc_lpspi0_clkdiv(self) -> Reg<LpspiClkdiv, RW>

LPSPI0 clock divider control

pub const fn mrcc_lpspi1_clksel(self) -> Reg<LpspiClksel, RW>

LPSPI1 clock selection control

pub const fn mrcc_lpspi1_clkdiv(self) -> Reg<LpspiClkdiv, RW>

LPSPI1 clock divider control

pub const fn mrcc_i3c2_fclk_clksel(self) -> Reg<I3cFclkClksel, RW>

I3C2_FCLK clock selection control

pub const fn mrcc_i3c2_fclk_clkdiv(self) -> Reg<I3cFclkClkdiv, RW>

I3C2_FCLK clock divider control

pub const fn mrcc_lpuart0_clksel(self) -> Reg<LpuartClksel, RW>

LPUART0 clock selection control

pub const fn mrcc_lpuart0_clkdiv(self) -> Reg<LpuartClkdiv, RW>

LPUART0 clock divider control

pub const fn mrcc_lpuart1_clksel(self) -> Reg<LpuartClksel, RW>

LPUART1 clock selection control

pub const fn mrcc_lpuart1_clkdiv(self) -> Reg<LpuartClkdiv, RW>

LPUART1 clock divider control

pub const fn mrcc_lpuart2_clksel(self) -> Reg<LpuartClksel, RW>

LPUART2 clock selection control

pub const fn mrcc_lpuart2_clkdiv(self) -> Reg<LpuartClkdiv, RW>

LPUART2 clock divider control

pub const fn mrcc_lpuart3_clksel(self) -> Reg<LpuartClksel, RW>

LPUART3 clock selection control

pub const fn mrcc_lpuart3_clkdiv(self) -> Reg<LpuartClkdiv, RW>

LPUART3 clock divider control

pub const fn mrcc_lpuart4_clksel(self) -> Reg<LpuartClksel, RW>

LPUART4 clock selection control

pub const fn mrcc_lpuart4_clkdiv(self) -> Reg<LpuartClkdiv, RW>

LPUART4 clock divider control

pub const fn mrcc_lptmr0_clksel(self) -> Reg<LptmrClksel, RW>

LPTMR0 clock selection control

pub const fn mrcc_lptmr0_clkdiv(self) -> Reg<LptmrClkdiv, RW>

LPTMR0 clock divider control

pub const fn mrcc_ostimer0_clksel(self) -> Reg<OstimerClksel, RW>

OSTIMER0 clock selection control

pub const fn mrcc_adc_clksel(self) -> Reg<MrccAdcClksel, RW>

ADCx clock selection control

pub const fn mrcc_adc_clkdiv(self) -> Reg<MrccAdcClkdiv, RW>

ADCx clock divider control

pub const fn mrcc_cmp0_func_clkdiv(self) -> Reg<CmpFuncClkdiv, RW>

CMP0_FUNC clock divider control

pub const fn mrcc_cmp0_rr_clksel(self) -> Reg<CmpRrClksel, RW>

CMP0_RR clock selection control

pub const fn mrcc_cmp0_rr_clkdiv(self) -> Reg<CmpRrClkdiv, RW>

CMP0_RR clock divider control

pub const fn mrcc_dac0_clksel(self) -> Reg<DacClksel, RW>

DAC0 clock selection control

pub const fn mrcc_dac0_clkdiv(self) -> Reg<DacClkdiv, RW>

DAC0 clock divider control

pub const fn mrcc_dac1_clksel(self) -> Reg<DacClksel, RW>

DAC1 clock selection control

pub const fn mrcc_dac1_clkdiv(self) -> Reg<DacClkdiv, RW>

DAC1 clock divider control

pub const fn mrcc_tsi0_clksel(self) -> Reg<TsiClksel, RW>

TSI0 clock selection control

pub const fn mrcc_tsi0_clkdiv(self) -> Reg<TsiClkdiv, RW>

TSI0 clock divider control

pub const fn mrcc_flexcan0_clksel(self) -> Reg<FlexcanClksel, RW>

FLEXCAN0 clock selection control

pub const fn mrcc_flexcan0_clkdiv(self) -> Reg<FlexcanClkdiv, RW>

FLEXCAN0 clock divider control

pub const fn mrcc_flexcan1_clksel(self) -> Reg<FlexcanClksel, RW>

FLEXCAN1 clock selection control

pub const fn mrcc_flexcan1_clkdiv(self) -> Reg<FlexcanClkdiv, RW>

FLEXCAN1 clock divider control

pub const fn mrcc_lpi2c2_clksel(self) -> Reg<Lpi2cClksel, RW>

LPI2C2 clock selection control

pub const fn mrcc_lpi2c2_clkdiv(self) -> Reg<Lpi2cClkdiv, RW>

LPI2C2 clock divider control

pub const fn mrcc_lpi2c3_clksel(self) -> Reg<Lpi2cClksel, RW>

LPI2C3 clock selection control

pub const fn mrcc_lpi2c3_clkdiv(self) -> Reg<Lpi2cClkdiv, RW>

LPI2C3 clock divider control

pub const fn mrcc_lpi2c4_clksel(self) -> Reg<Lpi2cClksel, RW>

LPI2C4 clock selection control

pub const fn mrcc_lpi2c4_clkdiv(self) -> Reg<Lpi2cClkdiv, RW>

LPI2C4 clock divider control

pub const fn mrcc_lpuart5_clksel(self) -> Reg<LpuartClksel, RW>

LPUART5 clock selection control

pub const fn mrcc_lpuart5_clkdiv(self) -> Reg<LpuartClkdiv, RW>

LPUART5 clock divider control

pub const fn mrcc_i3c3_fclk_clksel(self) -> Reg<I3cFclkClksel, RW>

I3C3_FCLK clock selection control

pub const fn mrcc_i3c3_fclk_clkdiv(self) -> Reg<I3cFclkClkdiv, RW>

I3C3_FCLK clock divider control

pub const fn mrcc_dbg_trace_clksel(self) -> Reg<MrccDbgTraceClksel, RW>

DBG_TRACE clock selection control

pub const fn mrcc_dbg_trace_clkdiv(self) -> Reg<MrccDbgTraceClkdiv, RW>

DBG_TRACE clock divider control

pub const fn mrcc_clkout_clksel(self) -> Reg<MrccClkoutClksel, RW>

CLKOUT clock selection control

pub const fn mrcc_clkout_clkdiv(self) -> Reg<MrccClkoutClkdiv, RW>

CLKOUT clock divider control

pub const fn mrcc_systick_clksel(self) -> Reg<MrccSystickClksel, RW>

SYSTICK clock selection control

pub const fn mrcc_systick_clkdiv(self) -> Reg<MrccSystickClkdiv, RW>

SYSTICK clock divider control

Trait Implementations

impl Clone for Mrcc

fn clone(&self) -> Mrcc

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Mrcc

fn eq(&self, other: &Mrcc) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Mrcc

impl Eq for Mrcc

impl Send for Mrcc

impl StructuralPartialEq for Mrcc

impl Sync for Mrcc