#[repr(u8)]pub enum ChargeNum {
Show 16 variants
CHARGE_NUM_0 = 0,
CHARGE_NUM_1 = 1,
CHARGE_NUM_2 = 2,
CHARGE_NUM_3 = 3,
CHARGE_NUM_4 = 4,
CHARGE_NUM_5 = 5,
CHARGE_NUM_6 = 6,
CHARGE_NUM_7 = 7,
CHARGE_NUM_8 = 8,
CHARGE_NUM_9 = 9,
CHARGE_NUM_10 = 10,
CHARGE_NUM_11 = 11,
CHARGE_NUM_12 = 12,
CHARGE_NUM_13 = 13,
CHARGE_NUM_14 = 14,
CHARGE_NUM_15 = 15,
}Variants§
CHARGE_NUM_0 = 0
The SSC output bit 0’s period will be 1 clock cycle of system clock
CHARGE_NUM_1 = 1
The SSC output bit 0’s period will be 2 clock cycles of system clock
CHARGE_NUM_2 = 2
The SSC output bit 0’s period will be 3 clock cycles of system clock
CHARGE_NUM_3 = 3
The SSC output bit 0’s period will be 4 clock cycles of system clock
CHARGE_NUM_4 = 4
The SSC output bit 0’s period will be 5 clock cycles of system clock
CHARGE_NUM_5 = 5
The SSC output bit 0’s period will be 6 clock cycles of system clock
CHARGE_NUM_6 = 6
The SSC output bit 0’s period will be 7 clock cycles of system clock
CHARGE_NUM_7 = 7
The SSC output bit 0’s period will be 8 clock cycles of system clock
CHARGE_NUM_8 = 8
The SSC output bit 0’s period will be 9 clock cycles of system clock
CHARGE_NUM_9 = 9
The SSC output bit 0’s period will be 10 clock cycles of system clock
CHARGE_NUM_10 = 10
The SSC output bit 0’s period will be 11 clock cycles of system clock
CHARGE_NUM_11 = 11
The SSC output bit 0’s period will be 12 clock cycles of system clock
CHARGE_NUM_12 = 12
The SSC output bit 0’s period will be 13 clock cycles of system clock
CHARGE_NUM_13 = 13
The SSC output bit 0’s period will be 14 clock cycles of system clock
CHARGE_NUM_14 = 14
The SSC output bit 0’s period will be 15 clock cycles of system clock
CHARGE_NUM_15 = 15
The SSC output bit 0’s period will be 16 clock cycles of system clock