Struct Enet0 

pub struct Enet0 { /* private fields */ }

ENET

Implementations

impl Enet0

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn mac_configuration(self) -> Reg<MacConfiguration, RW>

MAC Configuration

pub const fn mac_ext_configuration(self) -> Reg<MacExtConfiguration, RW>

MAC Extended Configuration Register

pub const fn mac_packet_filter(self) -> Reg<MacPacketFilter, RW>

MAC Packet Filter

pub const fn mac_watchdog_timeout(self) -> Reg<MacWatchdogTimeout, RW>

Watchdog Timeout

pub const fn mac_vlan_tag_ctrl(self) -> Reg<MacVlanTagCtrl, RW>

MAC VLAN Tag Control

pub const fn mac_vlan_incl(self) -> Reg<MacVlanIncl, RW>

VLAN Tag Inclusion or Replacement

pub const fn mac_inner_vlan_incl(self) -> Reg<MacInnerVlanIncl, RW>

MAC Inner VLAN Tag Inclusion or Replacement

pub const fn mac_q0_tx_flow_ctrl(self) -> Reg<MacQ0TxFlowCtrl, RW>

MAC Q0 Tx Flow Control

pub const fn mac_rx_flow_ctrl(self) -> Reg<MacRxFlowCtrl, RW>

MAC Rx Flow Control

pub const fn mac_rxq_ctrl4(self) -> Reg<MacRxqCtrl4, RW>

Receive Queue Control 4

pub const fn mac_rxq_ctrl0(self) -> Reg<MacRxqCtrl0, RW>

Receive Queue Control 0

pub const fn mac_rxq_ctrl1(self) -> Reg<MacRxqCtrl1, RW>

Receive Queue Control 1

pub const fn mac_rxq_ctrl2(self) -> Reg<MacRxqCtrl2, RW>

Receive Queue Control 2

pub const fn mac_interrupt_status(self) -> Reg<MacInterruptStatus, R>

Interrupt Status

pub const fn mac_interrupt_enable(self) -> Reg<MacInterruptEnable, RW>

Interrupt Enable

pub const fn mac_rx_tx_status(self) -> Reg<MacRxTxStatus, R>

Receive Transmit Status

pub const fn mac_pmt_control_status(self) -> Reg<MacPmtControlStatus, RW>

PMT Control and Status

pub const fn mac_rwk_packet_filter(self) -> Reg<MacRwkPacketFilter, RW>

Remote Wakeup Filter

pub const fn mac_lpi_control_status(self) -> Reg<MacLpiControlStatus, RW>

LPI Control and Status

pub const fn mac_lpi_timers_control(self) -> Reg<MacLpiTimersControl, RW>

LPI Timers Control

pub const fn mac_lpi_entry_timer(self) -> Reg<MacLpiEntryTimer, RW>

Tx LPI Entry Timer Control

pub const fn mac_oneus_tic_counter(self) -> Reg<MacOneusTicCounter, RW>

One-microsecond Reference Timer

pub const fn mac_version(self) -> Reg<MacVersion, R>

MAC Version

pub const fn mac_debug(self) -> Reg<MacDebug, R>

MAC Debug

pub const fn mac_hw_feature0(self) -> Reg<MacHwFeature0, R>

Hardware Features 0

pub const fn mac_hw_feature1(self) -> Reg<MacHwFeature1, R>

Hardware Features 1

pub const fn mac_hw_feature2(self) -> Reg<MacHwFeature2, R>

Hardware Features 2

pub const fn mac_hw_feature3(self) -> Reg<MacHwFeature3, R>

Hardware Features 3

pub const fn mac_mdio_address(self) -> Reg<MacMdioAddress, RW>

MDIO Address

pub const fn mac_mdio_data(self) -> Reg<MacMdioData, RW>

MAC MDIO Data

pub const fn mac_csr_sw_ctrl(self) -> Reg<MacCsrSwCtrl, RW>

CSR Software Control

pub const fn mac_address0_high(self) -> Reg<MacAddress0High, RW>

MAC Address0 High

pub const fn mac_address0_low(self) -> Reg<MacAddress0Low, RW>

MAC Address0 Low

pub const fn indir_access_ctrl(self) -> Reg<IndirAccessCtrl, RW>

Indirect Access Control

pub const fn indir_access_data(self) -> Reg<IndirAccessData, RW>

Indirect Access Data

pub const fn mac_timestamp_control(self) -> Reg<MacTimestampControl, RW>

Timestamp Control

pub const fn mac_sub_second_increment(self) -> Reg<MacSubSecondIncrement, RW>

Subsecond Increment

pub const fn mac_system_time_seconds(self) -> Reg<MacSystemTimeSeconds, R>

System Time Seconds

pub const fn mac_system_time_nanoseconds( self, ) -> Reg<MacSystemTimeNanoseconds, R>

System Time Nanoseconds

pub const fn mac_system_time_seconds_update( self, ) -> Reg<MacSystemTimeSecondsUpdate, RW>

System Time Seconds Update

pub const fn mac_system_time_nanoseconds_update( self, ) -> Reg<MacSystemTimeNanosecondsUpdate, RW>

System Time Nanoseconds Update

pub const fn mac_timestamp_addend(self) -> Reg<MacTimestampAddend, RW>

Timestamp Addend

pub const fn mac_timestamp_status(self) -> Reg<MacTimestampStatus, R>

Timestamp Status

pub const fn mac_tx_timestamp_status_nanoseconds( self, ) -> Reg<MacTxTimestampStatusNanoseconds, R>

Transmit Timestamp Status Nanoseconds

pub const fn mac_tx_timestamp_status_seconds( self, ) -> Reg<MacTxTimestampStatusSeconds, R>

Transmit Timestamp Status Seconds

pub const fn mac_timestamp_ingress_corr_nanosecond( self, ) -> Reg<MacTimestampIngressCorrNanosecond, RW>

Timestamp Ingress Correction Nanosecond

pub const fn mac_timestamp_egress_corr_nanosecond( self, ) -> Reg<MacTimestampEgressCorrNanosecond, RW>

Timestamp Egress Correction Nanosecond

pub const fn mac_timestamp_ingress_latency( self, ) -> Reg<MacTimestampIngressLatency, R>

Timestamp Ingress Latency

pub const fn mac_timestamp_egress_latency( self, ) -> Reg<MacTimestampEgressLatency, R>

Timestamp Egress Latency

pub const fn mac_pps_control(self) -> Reg<MacPpsControl, RW>

PPS Control

pub const fn pps0_target_time_seconds(self) -> Reg<Pps0TargetTimeSeconds, RW>

PPS0 Target Time Seconds

pub const fn pps0_target_time_nanoseconds( self, ) -> Reg<Pps0TargetTimeNanoseconds, RW>

PPS0 Target Time Nanoseconds

pub const fn mtl_operation_mode(self) -> Reg<MtlOperationMode, RW>

MTL Operation Mode

pub const fn mtl_interrupt_status(self) -> Reg<MtlInterruptStatus, R>

MTL Interrupt Status

pub const fn mtl_rxq_dma_map0(self) -> Reg<MtlRxqDmaMap0, RW>

Receive Queue and DMA Channel Mapping 0

pub const fn mtl_txq0_operation_mode(self) -> Reg<MtlTxq0OperationMode, RW>

Queue 0 Transmit Operation Mode

pub const fn mtl_txq0_underflow(self) -> Reg<MtlTxq0Underflow, R>

Queue 0 Underflow Counter

pub const fn mtl_txq0_debug(self) -> Reg<MtlTxq0Debug, R>

Queue 0 Transmit Debug

pub const fn mtl_txq0_ets_status(self) -> Reg<MtlTxq0EtsStatus, R>

Queue 0 ETS Status

pub const fn mtl_txq0_quantum_weight(self) -> Reg<MtlTxq0QuantumWeight, RW>

Queue 0 Quantum or Weights

pub const fn mtl_q0_interrupt_control_status( self, ) -> Reg<MtlQ0InterruptControlStatus, RW>

Queue 0 Interrupt Control Status

pub const fn mtl_rxq0_operation_mode(self) -> Reg<MtlRxq0OperationMode, RW>

Queue 0 Receive Operation Mode

pub const fn mtl_rxq0_missed_packet_overflow_cnt( self, ) -> Reg<MtlRxq0MissedPacketOverflowCnt, R>

Queue 0 Missed Packet and Overflow Counter

pub const fn mtl_rxq0_debug(self) -> Reg<MtlRxq0Debug, R>

Queue 0 Receive Debug

pub const fn mtl_rxq0_control(self) -> Reg<MtlRxq0Control, RW>

Queue 0 Receive Control

pub const fn mtl_txq1_operation_mode(self) -> Reg<MtlTxq1OperationMode, RW>

Queue 1 Transmit Operation Mode

pub const fn mtl_txq1_underflow(self) -> Reg<MtlTxq1Underflow, R>

Queue 1 Underflow Counter

pub const fn mtl_txq1_debug(self) -> Reg<MtlTxq1Debug, R>

Queue 1 Transmit Debug

pub const fn mtl_txq1_ets_control(self) -> Reg<MtlTxq1EtsControl, RW>

Queue 1 ETS Control

pub const fn mtl_txq1_ets_status(self) -> Reg<MtlTxq1EtsStatus, R>

Queue 1 ETS Status

pub const fn mtl_txq1_quantum_weight(self) -> Reg<MtlTxq1QuantumWeight, RW>

Queue 1 idleSlopeCredit, Quantum or Weights

pub const fn mtl_txq1_sendslopecredit(self) -> Reg<MtlTxq1Sendslopecredit, RW>

Queue 1 sendSlopeCredit

pub const fn mtl_txq1_hicredit(self) -> Reg<MtlTxq1Hicredit, RW>

Queue 1 hiCredit

pub const fn mtl_txq1_locredit(self) -> Reg<MtlTxq1Locredit, RW>

Queue 1 loCredit

pub const fn mtl_q1_interrupt_control_status( self, ) -> Reg<MtlQ1InterruptControlStatus, RW>

Queue 1 Interrupt Control Status

pub const fn mtl_rxq1_operation_mode(self) -> Reg<MtlRxq1OperationMode, RW>

Queue 1 Receive Operation Mode

pub const fn mtl_rxq1_missed_packet_overflow_cnt( self, ) -> Reg<MtlRxq1MissedPacketOverflowCnt, R>

Queue 1 Missed Packet and Overflow Counter

pub const fn mtl_rxq1_debug(self) -> Reg<MtlRxq1Debug, R>

Queue 1 Receive Debug

pub const fn mtl_rxq1_control(self) -> Reg<MtlRxq1Control, RW>

Queue 1 Receive Control

pub const fn dma_mode(self) -> Reg<DmaMode, RW>

DMA Bus Mode

pub const fn dma_sysbus_mode(self) -> Reg<DmaSysbusMode, RW>

DMA System Bus Mode

pub const fn dma_interrupt_status(self) -> Reg<DmaInterruptStatus, R>

DMA Interrupt Status

pub const fn dma_debug_status0(self) -> Reg<DmaDebugStatus0, R>

DMA Debug Status 0

pub const fn dma_ch0_control(self) -> Reg<DmaCh0Control, RW>

DMA Channel 0 Control

pub const fn dma_ch0_tx_control(self) -> Reg<DmaCh0TxControl, RW>

DMA Channel 0 Transmit Control

pub const fn dma_ch0_rx_control(self) -> Reg<DmaCh0RxControl, RW>

DMA Channel 0 Receive Control

pub const fn dma_ch0_txdesc_list_address( self, ) -> Reg<DmaCh0TxdescListAddress, RW>

Channel 0 Tx Descriptor List Address register

pub const fn dma_ch0_rxdesc_list_address( self, ) -> Reg<DmaCh0RxdescListAddress, RW>

Channel 0 Rx Descriptor List Address register

pub const fn dma_ch0_txdesc_tail_pointer( self, ) -> Reg<DmaCh0TxdescTailPointer, RW>

Channel 0 Tx Descriptor Tail Pointer

pub const fn dma_ch0_rxdesc_tail_pointer( self, ) -> Reg<DmaCh0RxdescTailPointer, RW>

Channel 0 Rx Descriptor Tail Pointer

pub const fn dma_ch0_txdesc_ring_length(self) -> Reg<DmaCh0TxdescRingLength, RW>

Channel 0 Tx Descriptor Ring Length

pub const fn dma_ch0_rx_control2(self) -> Reg<DmaCh0RxControl2, RW>

Channeli Receive Control

pub const fn dma_ch0_interrupt_enable(self) -> Reg<DmaCh0InterruptEnable, RW>

Channeli Interrupt Enable

pub const fn dma_ch0_rx_interrupt_watchdog_timer( self, ) -> Reg<DmaCh0RxInterruptWatchdogTimer, RW>

Channel 0 Receive Interrupt Watchdog Timer

pub const fn dma_ch0_slot_function_control_status( self, ) -> Reg<DmaCh0SlotFunctionControlStatus, RW>

Channel 0 Slot Function Control and Status

pub const fn dma_ch0_current_app_txdesc(self) -> Reg<DmaCh0CurrentAppTxdesc, R>

Channel 0 Current Application Transmit Descriptor

pub const fn dma_ch0_current_app_rxdesc(self) -> Reg<DmaCh0CurrentAppRxdesc, R>

Channel 0 Current Application Receive Descriptor

pub const fn dma_ch0_current_app_txbuffer( self, ) -> Reg<DmaCh0CurrentAppTxbuffer, R>

Channel 0 Current Application Transmit Buffer Address

pub const fn dma_ch0_current_app_rxbuffer( self, ) -> Reg<DmaCh0CurrentAppRxbuffer, R>

Channel 0 Current Application Receive Buffer Address

pub const fn dma_ch0_status(self) -> Reg<DmaCh0Status, RW>

DMA Channel 0 Status

pub const fn dma_ch0_miss_frame_cnt(self) -> Reg<DmaCh0MissFrameCnt, R>

Channel 0 Missed Frame Counter

pub const fn dma_ch0_rx_eri_cnt(self) -> Reg<DmaCh0RxEriCnt, R>

Channel 0 Receive ERI Counter

pub const fn dma_ch1_control(self) -> Reg<DmaCh1Control, RW>

DMA Channel 1 Control

pub const fn dma_ch1_tx_control(self) -> Reg<DmaCh1TxControl, RW>

DMA Channel 1 Transmit Control

pub const fn dma_ch1_rx_control(self) -> Reg<DmaCh1RxControl, RW>

DMA Channel 1 Receive Control

pub const fn dma_ch1_txdesc_list_address( self, ) -> Reg<DmaCh1TxdescListAddress, RW>

Channel 1 Tx Descriptor List Address

pub const fn dma_ch1_rxdesc_list_address( self, ) -> Reg<DmaCh1RxdescListAddress, RW>

Channel 1 Rx Descriptor List Address

pub const fn dma_ch1_txdesc_tail_pointer( self, ) -> Reg<DmaCh1TxdescTailPointer, RW>

Channel 1 Tx Descriptor Tail Pointer

pub const fn dma_ch1_rxdesc_tail_pointer( self, ) -> Reg<DmaCh1RxdescTailPointer, RW>

Channel 1 Rx Descriptor Tail Pointer

pub const fn dma_ch1_txdesc_ring_length(self) -> Reg<DmaCh1TxdescRingLength, RW>

Channel 1 Tx Descriptor Ring Length

pub const fn dma_ch1_rx_control2(self) -> Reg<DmaCh1RxControl2, RW>

DMA Channel 1 Receive Control

pub const fn dma_ch1_interrupt_enable(self) -> Reg<DmaCh1InterruptEnable, RW>

Channel 1 Interrupt Enable

pub const fn dma_ch1_rx_interrupt_watchdog_timer( self, ) -> Reg<DmaCh1RxInterruptWatchdogTimer, RW>

Channel 1 Receive Interrupt Watchdog Timer

pub const fn dma_ch1_slot_function_control_status( self, ) -> Reg<DmaCh1SlotFunctionControlStatus, RW>

Channel 1 Slot Function Control and Status

pub const fn dma_ch1_current_app_txdesc(self) -> Reg<DmaCh1CurrentAppTxdesc, R>

Channel 1 Current Application Transmit Descriptor

pub const fn dma_ch1_current_app_rxdesc(self) -> Reg<DmaCh1CurrentAppRxdesc, R>

Channel 1 Current Application Receive Descriptor

pub const fn dma_ch1_current_app_txbuffer( self, ) -> Reg<DmaCh1CurrentAppTxbuffer, R>

Channel 1 Current Application Transmit Buffer Address

pub const fn dma_ch1_current_app_rxbuffer( self, ) -> Reg<DmaCh1CurrentAppRxbuffer, R>

Channel 1 Current Application Receive Buffer Address

pub const fn dma_ch1_status(self) -> Reg<DmaCh1Status, RW>

DMA Channel 1 Status

pub const fn dma_ch1_miss_frame_cnt(self) -> Reg<DmaCh1MissFrameCnt, R>

Channel 1 Missed Frame Counter

pub const fn dma_ch1_rx_eri_cnt(self) -> Reg<DmaCh1RxEriCnt, R>

Channel 1 Receive ERI Counter

Trait Implementations

impl Clone for Enet0

fn clone(&self) -> Enet0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Enet0

fn eq(&self, other: &Enet0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Enet0

impl Eq for Enet0

impl Send for Enet0

impl StructuralPartialEq for Enet0

impl Sync for Enet0