Enum FlexPwm0SmExtaTrigin 

#[repr(u8)]
pub enum FlexPwm0SmExtaTrigin {
    VAL0 = 0,
    VAL1 = 1,
    VAL2 = 2,
    VAL3 = 3,
    VAL4 = 4,
    VAL5 = 5,
    VAL6 = 6,
    VAL7 = 7,
    VAL8 = 8,
    VAL9 = 9,
    _RESERVED_a = 10,
    VAL11 = 11,
    VAL12 = 12,
    VAL13 = 13,
    VAL14 = 14,
    VAL15 = 15,
    VAL16 = 16,
    VAL17 = 17,
    VAL18 = 18,
    VAL19 = 19,
    VAL20 = 20,
    VAL21 = 21,
    VAL22 = 22,
    VAL23 = 23,
    VAL24 = 24,
    VAL25 = 25,
    VAL26 = 26,
    VAL27 = 27,
    VAL28 = 28,
    VAL29 = 29,
    VAL30 = 30,
    VAL31 = 31,
    VAL32 = 32,
    VAL33 = 33,
    VAL34 = 34,
    VAL35 = 35,
    VAL36 = 36,
    VAL37 = 37,
    VAL38 = 38,
    VAL39 = 39,
    VAL40 = 40,
    VAL41 = 41,
    VAL42 = 42,
    VAL43 = 43,
    VAL44 = 44,
    VAL45 = 45,
    VAL46 = 46,
    VAL47 = 47,
    VAL48 = 48,
    VAL49 = 49,
    VAL50 = 50,
    VAL51 = 51,
    VAL52 = 52,
    VAL53 = 53,
    VAL54 = 54,
    VAL55 = 55,
    VAL56 = 56,
    VAL57 = 57,
    VAL58 = 58,
    VAL59 = 59,
    VAL60 = 60,
    _RESERVED_3d = 61,
    _RESERVED_3e = 62,
    _RESERVED_3f = 63,
}

Variants

VAL0 = 0

PINT PIN_INT0 input is selected

VAL1 = 1

PINT PIN_INT5 input is selected

VAL2 = 2

SCT_OUT4 input is selected

VAL3 = 3

SCT_OUT5 input is selected

VAL4 = 4

SCT_OUT2 input is selected

VAL5 = 5

CTIMER0_MAT3 input is selected

VAL6 = 6

CTIMER1_MAT3 input is selected

VAL7 = 7

CTIMER2_MAT3 input is selected

VAL8 = 8

CTIMER2_MAT0 input is selected

VAL9 = 9

CTIMER4_MAT0 input is selected

_RESERVED_a = 10

VAL11 = 11

ARM_TXEV input is selected

VAL12 = 12

PINT GPIO_INT_BMAT input is selected

VAL13 = 13

ADC0_tcomp[0] input is selected

VAL14 = 14

ADC0_tcomp[1] input is selected

VAL15 = 15

ADC0_tcomp[2] input is selected

VAL16 = 16

ADC0_tcomp[3] input is selected

VAL17 = 17

ADC1_tcomp[0] input is selected

VAL18 = 18

ADC1_tcomp[1] input is selected

VAL19 = 19

ADC1_tcomp[2] input is selected

VAL20 = 20

ADC1_tcomp[3] input is selected

VAL21 = 21

CMP0_OUT input is selected

VAL22 = 22

CMP1_OUT input is selected

VAL23 = 23

CMP2_OUT input is selected

VAL24 = 24

PWM1_SM0_MUX_TRIG0 input is selected

VAL25 = 25

PWM1_SM0_MUX_TRIG1 input is selected

VAL26 = 26

PWM1_SM1_MUX_TRIG0 input is selected

VAL27 = 27

PWM1_SM1_MUX_TRIG1 input is selected

VAL28 = 28

PWM1_SM2_MUX_TRIG0 input is selected

VAL29 = 29

PWM1_SM2_MUX_TRIG1 input is selected

VAL30 = 30

PWM1_SM3_MUX_TRIG0 input is selected

VAL31 = 31

PWM1_SM3_MUX_TRIG1 input is selected

VAL32 = 32

QDC0_CMP/POS_MATCH input is selected

VAL33 = 33

QDC1_CMP/POS_MATCH input is selected

VAL34 = 34

EVTG_OUT0A input is selected

VAL35 = 35

EVTG_OUT0B input is selected

VAL36 = 36

EVTG_OUT1A input is selected

VAL37 = 37

EVTG_OUT1B input is selected

VAL38 = 38

EVTG_OUT2A input is selected

VAL39 = 39

EVTG_OUT2B input is selected

VAL40 = 40

EVTG_OUT3A input is selected

VAL41 = 41

EVTG_OUT3B input is selected

VAL42 = 42

TRIG_IN0 input is selected

VAL43 = 43

TRIG_IN1 input is selected

VAL44 = 44

TRIG_IN2 input is selected

VAL45 = 45

TRIG_IN3 input is selected

VAL46 = 46

TRIG_IN4 input is selected

VAL47 = 47

TRIG_IN5 input is selected

VAL48 = 48

TRIG_IN6 input is selected

VAL49 = 49

TRIG_IN7 input is selected

VAL50 = 50

TRIG_IN8 input is selected

VAL51 = 51

TRIG_IN9 input is selected

VAL52 = 52

SINC Filter CH0 sync Break input is selected

VAL53 = 53

SINC Filter CH1 sync Break input is selected

VAL54 = 54

SINC Filter CH2 sync Break input is selected

VAL55 = 55

SINC Filter CH3 sync Break input is selected

VAL56 = 56

SINC Filter CH4 sync Break input is selected

VAL57 = 57

GPIO2 Pin Event Trig 0 input is selected

VAL58 = 58

GPIO2 Pin Event Trig 1 input is selected

VAL59 = 59

GPIO3 Pin Event Trig 0 input is selected

VAL60 = 60

GPIO3 Pin Event Trig 1 input is selected

_RESERVED_3d = 61

_RESERVED_3e = 62

_RESERVED_3f = 63

Implementations

impl FlexPwm0SmExtaTrigin

pub const fn from_bits(val: u8) -> FlexPwm0SmExtaTrigin

pub const fn to_bits(self) -> u8

Trait Implementations

impl Clone for FlexPwm0SmExtaTrigin

fn clone(&self) -> FlexPwm0SmExtaTrigin

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for FlexPwm0SmExtaTrigin

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<FlexPwm0SmExtaTrigin> for u8

fn from(val: FlexPwm0SmExtaTrigin) -> u8

Converts to this type from the input type.

impl From<u8> for FlexPwm0SmExtaTrigin

fn from(val: u8) -> FlexPwm0SmExtaTrigin

Converts to this type from the input type.

impl Ord for FlexPwm0SmExtaTrigin

fn cmp(&self, other: &FlexPwm0SmExtaTrigin) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Self

where Self: Sized,

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Self

where Self: Sized,

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Self

where Self: Sized,

Restrict a value to a certain interval.

impl PartialEq for FlexPwm0SmExtaTrigin

fn eq(&self, other: &FlexPwm0SmExtaTrigin) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl PartialOrd for FlexPwm0SmExtaTrigin

fn partial_cmp(&self, other: &FlexPwm0SmExtaTrigin) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

Tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

Tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

Tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

Tests greater than or equal to (for self and other) and is used by the >= operator.

impl Copy for FlexPwm0SmExtaTrigin

impl Eq for FlexPwm0SmExtaTrigin

impl StructuralPartialEq for FlexPwm0SmExtaTrigin