Struct ElsAsCfg1 

#[repr(transparent)]
pub struct ElsAsCfg1(pub u32);

ELS AS Configuration1

Tuple Fields

0: u32

Implementations

impl ElsAsCfg1

pub const fn cfg_sec_dis_strict_mode(&self) -> bool

When CFG_SEC_ENA_SEC_CHK indicates state 0 or when DISABLE_STRICT_MODE bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are equal to 01, this bit indicates state 1

pub const fn set_cfg_sec_dis_strict_mode(&mut self, val: bool)

When CFG_SEC_ENA_SEC_CHK indicates state 0 or when DISABLE_STRICT_MODE bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are equal to 01, this bit indicates state 1

pub const fn cfg_sec_dis_viol_abort(&self) -> bool

When the DISABLE_VIOLATION_ABORT bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn set_cfg_sec_dis_viol_abort(&mut self, val: bool)

When the DISABLE_VIOLATION_ABORT bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn cfg_sec_ena_ns_priv_chk(&self) -> bool

When the ENABLE_NS_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn set_cfg_sec_ena_ns_priv_chk(&mut self, val: bool)

When the ENABLE_NS_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn cfg_sec_ena_s_priv_chk(&self) -> bool

When the ENABLE_S_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn set_cfg_sec_ena_s_priv_chk(&mut self, val: bool)

When the ENABLE_S_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn cfg_sec_ena_sec_chk(&self) -> bool

When the ENABLE_SECURE_CHECKING bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn set_cfg_sec_ena_sec_chk(&mut self, val: bool)

When the ENABLE_SECURE_CHECKING bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn cfg_sec_idau_allns(&self) -> bool

When the IDAU_ALL_NS bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are equal to 01, this bit indicates state 1

pub const fn set_cfg_sec_idau_allns(&mut self, val: bool)

When the IDAU_ALL_NS bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are equal to 01, this bit indicates state 1

pub const fn cfg_sec_lock_ns_mpu(&self) -> bool

When the LOCK_NS_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn set_cfg_sec_lock_ns_mpu(&mut self, val: bool)

When the LOCK_NS_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn cfg_sec_lock_ns_vtor(&self) -> bool

When the LOCK_NS_VTOR bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn set_cfg_sec_lock_ns_vtor(&mut self, val: bool)

When the LOCK_NS_VTOR bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn cfg_sec_lock_s_mpu(&self) -> bool

When the LOCK_S_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn set_cfg_sec_lock_s_mpu(&mut self, val: bool)

When the LOCK_S_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn cfg_sec_lock_s_vtaircr(&self) -> bool

When the LOCK_S_VTAIRCR bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn set_cfg_sec_lock_s_vtaircr(&mut self, val: bool)

When the LOCK_S_VTAIRCR bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn cfg_sec_lock_sau(&self) -> bool

When the LOCK_SAU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn set_cfg_sec_lock_sau(&mut self, val: bool)

When the LOCK_SAU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1

pub const fn metal_version(&self) -> u8

metal version

pub const fn set_metal_version(&mut self, val: u8)

metal version

pub const fn rom_patch_version(&self) -> u8

ROM patch version

pub const fn set_rom_patch_version(&mut self, val: u8)

ROM patch version

pub const fn cfg_hvd_core_reset_enabled(&self) -> bool

When SPC CORE HVD analog detector are turned on, and CORE HVD reset are enabled, this bit indicates state 1.

pub const fn set_cfg_hvd_core_reset_enabled(&mut self, val: bool)

When SPC CORE HVD analog detector are turned on, and CORE HVD reset are enabled, this bit indicates state 1.

pub const fn cfg_hvd_core_irq_enabled(&self) -> bool

When SPC CORE HVD analog detector are turned on, and CORE HVD IRQ are enabled, this bit indicates state 1.

pub const fn set_cfg_hvd_core_irq_enabled(&mut self, val: bool)

When SPC CORE HVD analog detector are turned on, and CORE HVD IRQ are enabled, this bit indicates state 1.

pub const fn cfg_hvd_vsys_reset_enabled(&self) -> bool

When SPC VSYS HVD analog detector are turned on and VSYS HVD reset are enabled, this bit indicates state 1.

pub const fn set_cfg_hvd_vsys_reset_enabled(&mut self, val: bool)

When SPC VSYS HVD analog detector are turned on and VSYS HVD reset are enabled, this bit indicates state 1.

pub const fn cfg_hvd_vddio_reset_enabled(&self) -> bool

When SPC VDDIO HVD analog detector are turned on and VDDIO HVD reset are enabled, this bit indicates state 1.

pub const fn set_cfg_hvd_vddio_reset_enabled(&mut self, val: bool)

When SPC VDDIO HVD analog detector are turned on and VDDIO HVD reset are enabled, this bit indicates state 1.

pub const fn cfg_hvd_vsys_irq_enabled(&self) -> bool

When SPC VSYS HVD analog detector are turned on and VSYS HVD irq are enabled, this bit indicates state 1.

pub const fn set_cfg_hvd_vsys_irq_enabled(&mut self, val: bool)

When SPC VSYS HVD analog detector are turned on and VSYS HVD irq are enabled, this bit indicates state 1.

pub const fn cfg_hvd_vddio_irq_enabled(&self) -> bool

When SPC VDDIO HVD analog detector are turned on and VDDIO HVD irq are enabled, this bit indicates state 1.

pub const fn set_cfg_hvd_vddio_irq_enabled(&mut self, val: bool)

When SPC VDDIO HVD analog detector are turned on and VDDIO HVD irq are enabled, this bit indicates state 1.

Trait Implementations

impl Clone for ElsAsCfg1

fn clone(&self) -> ElsAsCfg1

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ElsAsCfg1

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for ElsAsCfg1

fn default() -> ElsAsCfg1

Returns the “default value” for a type.

impl PartialEq for ElsAsCfg1

fn eq(&self, other: &ElsAsCfg1) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for ElsAsCfg1

impl Eq for ElsAsCfg1

impl StructuralPartialEq for ElsAsCfg1