Struct ElsAsFlag0 

#[repr(transparent)]
pub struct ElsAsFlag0(pub u32);

ELS AS Flag0

Tuple Fields

0: u32

Implementations

impl ElsAsFlag0

pub const fn flag_ap_enable_cpu0(&self) -> bool

This flag bit is set as 1 when DAP enables AP0 for CPU0 (CM33) debug access. The register is cleared 0 by PMC reset event.

pub const fn set_flag_ap_enable_cpu0(&mut self, val: bool)

This flag bit is set as 1 when DAP enables AP0 for CPU0 (CM33) debug access. The register is cleared 0 by PMC reset event.

pub const fn flag_ap_enable_cpu1(&self) -> bool

This flag bit is set as 1 when DAP enables AP1 for CPU1 (CM33) debug access. The register is cleared 0 by PMC reset event.

pub const fn set_flag_ap_enable_cpu1(&mut self, val: bool)

This flag bit is set as 1 when DAP enables AP1 for CPU1 (CM33) debug access. The register is cleared 0 by PMC reset event.

pub const fn flag_ap_enable_dsp(&self) -> bool

This flag bit is set as 1 when DAP enables AP3 for DSP (CoolFlux) debug access. The register is cleared 0 by PMC reset event.

pub const fn set_flag_ap_enable_dsp(&mut self, val: bool)

This flag bit is set as 1 when DAP enables AP3 for DSP (CoolFlux) debug access. The register is cleared 0 by PMC reset event.

pub const fn efuse_attack_detect(&self) -> bool

OTPC can output attack_detect signal when it detects attack when load shadow registers. The output will be cleared by reset. ELS_AS_FLAG is reset by PoR, so the status can be recorded.

pub const fn set_efuse_attack_detect(&mut self, val: bool)

OTPC can output attack_detect signal when it detects attack when load shadow registers. The output will be cleared by reset. ELS_AS_FLAG is reset by PoR, so the status can be recorded.

pub const fn flag_lvd_core_occured(&self) -> bool

This flag register is set 1 when VDD_CORE LVD event is triggered. This register is cleared 0 by PMC reset event.

pub const fn set_flag_lvd_core_occured(&mut self, val: bool)

This flag register is set 1 when VDD_CORE LVD event is triggered. This register is cleared 0 by PMC reset event.

pub const fn flag_wdt0_reset_occured(&self) -> bool

This flag bit is set as 1 when WatchDog Timer 0 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.

pub const fn set_flag_wdt0_reset_occured(&mut self, val: bool)

This flag bit is set as 1 when WatchDog Timer 0 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.

pub const fn flag_cwdt0_reset_occured(&self) -> bool

This flag bit is set as 1 when Code WatchDog Timer 0 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.

pub const fn set_flag_cwdt0_reset_occured(&mut self, val: bool)

This flag bit is set as 1 when Code WatchDog Timer 0 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.

pub const fn flag_wdt0_irq_occured(&self) -> bool

This flag bit is set as 1 when WatchDog Timer 0 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn set_flag_wdt0_irq_occured(&mut self, val: bool)

This flag bit is set as 1 when WatchDog Timer 0 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn flag_cwdt0_irq_occured(&self) -> bool

This flag bit is set as 1 when Code WatchDog Timer 0 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn set_flag_cwdt0_irq_occured(&mut self, val: bool)

This flag bit is set as 1 when Code WatchDog Timer 0 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn flag_qk_error(&self) -> bool

This flag bit is set as 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event.

pub const fn set_flag_qk_error(&mut self, val: bool)

This flag bit is set as 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event.

pub const fn flag_els_glitch_detected(&self) -> bool

This flag bit is set as 1 when GDET error is flagged. This register is cleared 0 by PMC reset event.

pub const fn set_flag_els_glitch_detected(&mut self, val: bool)

This flag bit is set as 1 when GDET error is flagged. This register is cleared 0 by PMC reset event.

pub const fn flag_ana_glitch_detected(&self) -> bool

This flag bit is set as 1 when ANALOG GDET error is flagged in SYSCON block. This register is cleared 0 by PMC reset event.

pub const fn set_flag_ana_glitch_detected(&mut self, val: bool)

This flag bit is set as 1 when ANALOG GDET error is flagged in SYSCON block. This register is cleared 0 by PMC reset event.

pub const fn flag_tamper_event_detected(&self) -> bool

This flag bit is set as 1 when tamper event is flagged from TDET. This register is cleared 0 by AO domain POR or by PMC reset event, if tamper detection event is cleared by software.

pub const fn set_flag_tamper_event_detected(&mut self, val: bool)

This flag bit is set as 1 when tamper event is flagged from TDET. This register is cleared 0 by AO domain POR or by PMC reset event, if tamper detection event is cleared by software.

pub const fn flag_flash_ecc_invalid(&self) -> bool

This flag bit is set as 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event.

pub const fn set_flag_flash_ecc_invalid(&mut self, val: bool)

This flag bit is set as 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event.

pub const fn flag_sec_viol_irq_ocurred(&self) -> bool

This flag bit is set as 1 when security violation is indicated from FLASH sub-system or AHB bus matrix.

pub const fn set_flag_sec_viol_irq_ocurred(&mut self, val: bool)

This flag bit is set as 1 when security violation is indicated from FLASH sub-system or AHB bus matrix.

pub const fn flag_cpu0_ns_c_acc_occured(&self) -> bool

This flag bit is set as 1 when CPU0 (CM33) makes non-secure code transactions. This register is cleared 0 by PMC reset event.

pub const fn set_flag_cpu0_ns_c_acc_occured(&mut self, val: bool)

This flag bit is set as 1 when CPU0 (CM33) makes non-secure code transactions. This register is cleared 0 by PMC reset event.

pub const fn flag_cpu0_ns_d_acc_occured(&self) -> bool

This flag bit is set as 1 when CPU0 (CM33) makes non-secure data transactions. This register is cleared 0 by PMC reset event.

pub const fn set_flag_cpu0_ns_d_acc_occured(&mut self, val: bool)

This flag bit is set as 1 when CPU0 (CM33) makes non-secure data transactions. This register is cleared 0 by PMC reset event.

pub const fn flag_lvd_vsys_occured(&self) -> bool

This flag register is set 1 when VDD_SYS LVD event is triggered. This register is cleared 0 by PMC reset event.

pub const fn set_flag_lvd_vsys_occured(&mut self, val: bool)

This flag register is set 1 when VDD_SYS LVD event is triggered. This register is cleared 0 by PMC reset event.

pub const fn flag_lvd_vddio_occured(&self) -> bool

This flag register is set 1 when VDD LVD event is triggered. This register is cleared 0 by PMC reset event.

pub const fn set_flag_lvd_vddio_occured(&mut self, val: bool)

This flag register is set 1 when VDD LVD event is triggered. This register is cleared 0 by PMC reset event.

pub const fn flag_wdt1_reset_occured(&self) -> bool

This flag bit is set as 1 when WatchDog Timer 1 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.

pub const fn set_flag_wdt1_reset_occured(&mut self, val: bool)

This flag bit is set as 1 when WatchDog Timer 1 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.

pub const fn flag_cwdt1_reset_occured(&self) -> bool

This flag bit is set as 1 when Code WatchDog Timer 1 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.

pub const fn set_flag_cwdt1_reset_occured(&mut self, val: bool)

This flag bit is set as 1 when Code WatchDog Timer 1 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.

pub const fn flag_wdt1_irq_occured(&self) -> bool

This flag bit is set as 1 when WatchDog Timer 1 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn set_flag_wdt1_irq_occured(&mut self, val: bool)

This flag bit is set as 1 when WatchDog Timer 1 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn flag_cwdt1_irq_occured(&self) -> bool

This flag bit is set as 1 when Code WatchDog Timer 1 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn set_flag_cwdt1_irq_occured(&mut self, val: bool)

This flag bit is set as 1 when Code WatchDog Timer 1 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn flag_temptamper_det_irq_occured(&self) -> bool

This flag bit is set as 1 when temperature temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn set_flag_temptamper_det_irq_occured(&mut self, val: bool)

This flag bit is set as 1 when temperature temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn flag_voltamper_det_irq_occured(&self) -> bool

This flag bit is set as 1 when voltage temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn set_flag_voltamper_det_irq_occured(&mut self, val: bool)

This flag bit is set as 1 when voltage temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn flag_lhttamper_det_irq_occured(&self) -> bool

This flag bit is set as 1 when light temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn set_flag_lhttamper_det_irq_occured(&mut self, val: bool)

This flag bit is set as 1 when light temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn flag_clktamper_det_irq_occured(&self) -> bool

This flag bit is set as 1 when clock temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

pub const fn set_flag_clktamper_det_irq_occured(&mut self, val: bool)

This flag bit is set as 1 when clock temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.

Trait Implementations

impl Clone for ElsAsFlag0

fn clone(&self) -> ElsAsFlag0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ElsAsFlag0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for ElsAsFlag0

fn default() -> ElsAsFlag0

Returns the “default value” for a type.

impl PartialEq for ElsAsFlag0

fn eq(&self, other: &ElsAsFlag0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for ElsAsFlag0

impl Eq for ElsAsFlag0

impl StructuralPartialEq for ElsAsFlag0