Struct Pwm 

pub struct Pwm { /* private fields */ }

PWM

Implementations

impl Pwm

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn sm0cnt(self) -> Reg<Sm0cnt, R>

Counter Register

pub const fn sm0init(self) -> Reg<Sm0init, RW>

Initial Count Register

pub const fn sm0ctrl2(self) -> Reg<Sm0ctrl2, RW>

Control 2 Register

pub const fn sm0ctrl(self) -> Reg<Sm0ctrl, RW>

Control Register

pub const fn sm0val0(self) -> Reg<Sm0val0, RW>

Value Register 0

pub const fn sm0fracval1(self) -> Reg<Sm0fracval1, RW>

Fractional Value Register 1

pub const fn sm0val1(self) -> Reg<Sm0val1, RW>

Value Register 1

pub const fn sm0fracval2(self) -> Reg<Sm0fracval2, RW>

Fractional Value Register 2

pub const fn sm0val2(self) -> Reg<Sm0val2, RW>

Value Register 2

pub const fn sm0fracval3(self) -> Reg<Sm0fracval3, RW>

Fractional Value Register 3

pub const fn sm0val3(self) -> Reg<Sm0val3, RW>

Value Register 3

pub const fn sm0fracval4(self) -> Reg<Sm0fracval4, RW>

Fractional Value Register 4

pub const fn sm0val4(self) -> Reg<Sm0val4, RW>

Value Register 4

pub const fn sm0fracval5(self) -> Reg<Sm0fracval5, RW>

Fractional Value Register 5

pub const fn sm0val5(self) -> Reg<Sm0val5, RW>

Value Register 5

pub const fn sm0frctrl(self) -> Reg<Sm0frctrl, RW>

Fractional Control Register

pub const fn sm0octrl(self) -> Reg<Sm0octrl, RW>

Output Control Register

pub const fn sm0sts(self) -> Reg<Sm0sts, RW>

Status Register

pub const fn sm0inten(self) -> Reg<Sm0inten, RW>

Interrupt Enable Register

pub const fn sm0dmaen(self) -> Reg<Sm0dmaen, RW>

DMA Enable Register

pub const fn sm0tctrl(self) -> Reg<Sm0tctrl, RW>

Output Trigger Control Register

pub const fn sm0dismap0(self) -> Reg<Sm0dismap0, RW>

Fault Disable Mapping Register 0

pub const fn sm0dtcnt0(self) -> Reg<Sm0dtcnt0, RW>

Deadtime Count Register 0

pub const fn sm0dtcnt1(self) -> Reg<Sm0dtcnt1, RW>

Deadtime Count Register 1

pub const fn sm0captctrla(self) -> Reg<Sm0captctrla, RW>

Capture Control A Register

pub const fn sm0captcompa(self) -> Reg<Sm0captcompa, RW>

Capture Compare A Register

pub const fn sm0captctrlb(self) -> Reg<Sm0captctrlb, RW>

Capture Control B Register

pub const fn sm0captcompb(self) -> Reg<Sm0captcompb, RW>

Capture Compare B Register

pub const fn sm0captctrlx(self) -> Reg<Sm0captctrlx, RW>

Capture Control X Register

pub const fn sm0captcompx(self) -> Reg<Sm0captcompx, RW>

Capture Compare X Register

pub const fn sm0cval0(self) -> Reg<Sm0cval0, R>

Capture Value 0 Register

pub const fn sm0cval0cyc(self) -> Reg<Sm0cval0cyc, R>

Capture Value 0 Cycle Register

pub const fn sm0cval1(self) -> Reg<Sm0cval1, R>

Capture Value 1 Register

pub const fn sm0cval1cyc(self) -> Reg<Sm0cval1cyc, R>

Capture Value 1 Cycle Register

pub const fn sm0cval2(self) -> Reg<Sm0cval2, R>

Capture Value 2 Register

pub const fn sm0cval2cyc(self) -> Reg<Sm0cval2cyc, R>

Capture Value 2 Cycle Register

pub const fn sm0cval3(self) -> Reg<Sm0cval3, R>

Capture Value 3 Register

pub const fn sm0cval3cyc(self) -> Reg<Sm0cval3cyc, R>

Capture Value 3 Cycle Register

pub const fn sm0cval4(self) -> Reg<Sm0cval4, R>

Capture Value 4 Register

pub const fn sm0cval4cyc(self) -> Reg<Sm0cval4cyc, R>

Capture Value 4 Cycle Register

pub const fn sm0cval5(self) -> Reg<Sm0cval5, R>

Capture Value 5 Register

pub const fn sm0cval5cyc(self) -> Reg<Sm0cval5cyc, R>

Capture Value 5 Cycle Register

pub const fn sm0captfilta(self) -> Reg<Sm0captfilta, RW>

Capture PWM_A Input Filter Register

pub const fn sm0captfiltb(self) -> Reg<Sm0captfiltb, RW>

Capture PWM_B Input Filter Register

pub const fn sm0captfiltx(self) -> Reg<Sm0captfiltx, RW>

Capture PWM_X Input Filter Register

pub const fn sm1cnt(self) -> Reg<Sm1cnt, R>

Counter Register

pub const fn sm1init(self) -> Reg<Sm1init, RW>

Initial Count Register

pub const fn sm1ctrl2(self) -> Reg<Sm1ctrl2, RW>

Control 2 Register

pub const fn sm1ctrl(self) -> Reg<Sm1ctrl, RW>

Control Register

pub const fn sm1val0(self) -> Reg<Sm1val0, RW>

Value Register 0

pub const fn sm1fracval1(self) -> Reg<Sm1fracval1, RW>

Fractional Value Register 1

pub const fn sm1val1(self) -> Reg<Sm1val1, RW>

Value Register 1

pub const fn sm1fracval2(self) -> Reg<Sm1fracval2, RW>

Fractional Value Register 2

pub const fn sm1val2(self) -> Reg<Sm1val2, RW>

Value Register 2

pub const fn sm1fracval3(self) -> Reg<Sm1fracval3, RW>

Fractional Value Register 3

pub const fn sm1val3(self) -> Reg<Sm1val3, RW>

Value Register 3

pub const fn sm1fracval4(self) -> Reg<Sm1fracval4, RW>

Fractional Value Register 4

pub const fn sm1val4(self) -> Reg<Sm1val4, RW>

Value Register 4

pub const fn sm1fracval5(self) -> Reg<Sm1fracval5, RW>

Fractional Value Register 5

pub const fn sm1val5(self) -> Reg<Sm1val5, RW>

Value Register 5

pub const fn sm1frctrl(self) -> Reg<Sm1frctrl, RW>

Fractional Control Register

pub const fn sm1octrl(self) -> Reg<Sm1octrl, RW>

Output Control Register

pub const fn sm1sts(self) -> Reg<Sm1sts, RW>

Status Register

pub const fn sm1inten(self) -> Reg<Sm1inten, RW>

Interrupt Enable Register

pub const fn sm1dmaen(self) -> Reg<Sm1dmaen, RW>

DMA Enable Register

pub const fn sm1tctrl(self) -> Reg<Sm1tctrl, RW>

Output Trigger Control Register

pub const fn sm1dismap0(self) -> Reg<Sm1dismap0, RW>

Fault Disable Mapping Register 0

pub const fn sm1dtcnt0(self) -> Reg<Sm1dtcnt0, RW>

Deadtime Count Register 0

pub const fn sm1dtcnt1(self) -> Reg<Sm1dtcnt1, RW>

Deadtime Count Register 1

pub const fn sm1captctrla(self) -> Reg<Sm1captctrla, RW>

Capture Control A Register

pub const fn sm1captcompa(self) -> Reg<Sm1captcompa, RW>

Capture Compare A Register

pub const fn sm1captctrlb(self) -> Reg<Sm1captctrlb, RW>

Capture Control B Register

pub const fn sm1captcompb(self) -> Reg<Sm1captcompb, RW>

Capture Compare B Register

pub const fn sm1captctrlx(self) -> Reg<Sm1captctrlx, RW>

Capture Control X Register

pub const fn sm1captcompx(self) -> Reg<Sm1captcompx, RW>

Capture Compare X Register

pub const fn sm1cval0(self) -> Reg<Sm1cval0, R>

Capture Value 0 Register

pub const fn sm1cval0cyc(self) -> Reg<Sm1cval0cyc, R>

Capture Value 0 Cycle Register

pub const fn sm1cval1(self) -> Reg<Sm1cval1, R>

Capture Value 1 Register

pub const fn sm1cval1cyc(self) -> Reg<Sm1cval1cyc, R>

Capture Value 1 Cycle Register

pub const fn sm1cval2(self) -> Reg<Sm1cval2, R>

Capture Value 2 Register

pub const fn sm1cval2cyc(self) -> Reg<Sm1cval2cyc, R>

Capture Value 2 Cycle Register

pub const fn sm1cval3(self) -> Reg<Sm1cval3, R>

Capture Value 3 Register

pub const fn sm1cval3cyc(self) -> Reg<Sm1cval3cyc, R>

Capture Value 3 Cycle Register

pub const fn sm1cval4(self) -> Reg<Sm1cval4, R>

Capture Value 4 Register

pub const fn sm1cval4cyc(self) -> Reg<Sm1cval4cyc, R>

Capture Value 4 Cycle Register

pub const fn sm1cval5(self) -> Reg<Sm1cval5, R>

Capture Value 5 Register

pub const fn sm1cval5cyc(self) -> Reg<Sm1cval5cyc, R>

Capture Value 5 Cycle Register

pub const fn sm1phasedly(self) -> Reg<Sm1phasedly, RW>

Phase Delay Register

pub const fn sm1captfilta(self) -> Reg<Sm1captfilta, RW>

Capture PWM_A Input Filter Register

pub const fn sm1captfiltb(self) -> Reg<Sm1captfiltb, RW>

Capture PWM_B Input Filter Register

pub const fn sm1captfiltx(self) -> Reg<Sm1captfiltx, RW>

Capture PWM_X Input Filter Register

pub const fn sm2cnt(self) -> Reg<Sm2cnt, R>

Counter Register

pub const fn sm2init(self) -> Reg<Sm2init, RW>

Initial Count Register

pub const fn sm2ctrl2(self) -> Reg<Sm2ctrl2, RW>

Control 2 Register

pub const fn sm2ctrl(self) -> Reg<Sm2ctrl, RW>

Control Register

pub const fn sm2val0(self) -> Reg<Sm2val0, RW>

Value Register 0

pub const fn sm2fracval1(self) -> Reg<Sm2fracval1, RW>

Fractional Value Register 1

pub const fn sm2val1(self) -> Reg<Sm2val1, RW>

Value Register 1

pub const fn sm2fracval2(self) -> Reg<Sm2fracval2, RW>

Fractional Value Register 2

pub const fn sm2val2(self) -> Reg<Sm2val2, RW>

Value Register 2

pub const fn sm2fracval3(self) -> Reg<Sm2fracval3, RW>

Fractional Value Register 3

pub const fn sm2val3(self) -> Reg<Sm2val3, RW>

Value Register 3

pub const fn sm2fracval4(self) -> Reg<Sm2fracval4, RW>

Fractional Value Register 4

pub const fn sm2val4(self) -> Reg<Sm2val4, RW>

Value Register 4

pub const fn sm2fracval5(self) -> Reg<Sm2fracval5, RW>

Fractional Value Register 5

pub const fn sm2val5(self) -> Reg<Sm2val5, RW>

Value Register 5

pub const fn sm2frctrl(self) -> Reg<Sm2frctrl, RW>

Fractional Control Register

pub const fn sm2octrl(self) -> Reg<Sm2octrl, RW>

Output Control Register

pub const fn sm2sts(self) -> Reg<Sm2sts, RW>

Status Register

pub const fn sm2inten(self) -> Reg<Sm2inten, RW>

Interrupt Enable Register

pub const fn sm2dmaen(self) -> Reg<Sm2dmaen, RW>

DMA Enable Register

pub const fn sm2tctrl(self) -> Reg<Sm2tctrl, RW>

Output Trigger Control Register

pub const fn sm2dismap0(self) -> Reg<Sm2dismap0, RW>

Fault Disable Mapping Register 0

pub const fn sm2dtcnt0(self) -> Reg<Sm2dtcnt0, RW>

Deadtime Count Register 0

pub const fn sm2dtcnt1(self) -> Reg<Sm2dtcnt1, RW>

Deadtime Count Register 1

pub const fn sm2captctrla(self) -> Reg<Sm2captctrla, RW>

Capture Control A Register

pub const fn sm2captcompa(self) -> Reg<Sm2captcompa, RW>

Capture Compare A Register

pub const fn sm2captctrlb(self) -> Reg<Sm2captctrlb, RW>

Capture Control B Register

pub const fn sm2captcompb(self) -> Reg<Sm2captcompb, RW>

Capture Compare B Register

pub const fn sm2captctrlx(self) -> Reg<Sm2captctrlx, RW>

Capture Control X Register

pub const fn sm2captcompx(self) -> Reg<Sm2captcompx, RW>

Capture Compare X Register

pub const fn sm2cval0(self) -> Reg<Sm2cval0, R>

Capture Value 0 Register

pub const fn sm2cval0cyc(self) -> Reg<Sm2cval0cyc, R>

Capture Value 0 Cycle Register

pub const fn sm2cval1(self) -> Reg<Sm2cval1, R>

Capture Value 1 Register

pub const fn sm2cval1cyc(self) -> Reg<Sm2cval1cyc, R>

Capture Value 1 Cycle Register

pub const fn sm2cval2(self) -> Reg<Sm2cval2, R>

Capture Value 2 Register

pub const fn sm2cval2cyc(self) -> Reg<Sm2cval2cyc, R>

Capture Value 2 Cycle Register

pub const fn sm2cval3(self) -> Reg<Sm2cval3, R>

Capture Value 3 Register

pub const fn sm2cval3cyc(self) -> Reg<Sm2cval3cyc, R>

Capture Value 3 Cycle Register

pub const fn sm2cval4(self) -> Reg<Sm2cval4, R>

Capture Value 4 Register

pub const fn sm2cval4cyc(self) -> Reg<Sm2cval4cyc, R>

Capture Value 4 Cycle Register

pub const fn sm2cval5(self) -> Reg<Sm2cval5, R>

Capture Value 5 Register

pub const fn sm2cval5cyc(self) -> Reg<Sm2cval5cyc, R>

Capture Value 5 Cycle Register

pub const fn sm2phasedly(self) -> Reg<Sm2phasedly, RW>

Phase Delay Register

pub const fn sm2captfilta(self) -> Reg<Sm2captfilta, RW>

Capture PWM_A Input Filter Register

pub const fn sm2captfiltb(self) -> Reg<Sm2captfiltb, RW>

Capture PWM_B Input Filter Register

pub const fn sm2captfiltx(self) -> Reg<Sm2captfiltx, RW>

Capture PWM_X Input Filter Register

pub const fn sm3cnt(self) -> Reg<Sm3cnt, R>

Counter Register

pub const fn sm3init(self) -> Reg<Sm3init, RW>

Initial Count Register

pub const fn sm3ctrl2(self) -> Reg<Sm3ctrl2, RW>

Control 2 Register

pub const fn sm3ctrl(self) -> Reg<Sm3ctrl, RW>

Control Register

pub const fn sm3val0(self) -> Reg<Sm3val0, RW>

Value Register 0

pub const fn sm3fracval1(self) -> Reg<Sm3fracval1, RW>

Fractional Value Register 1

pub const fn sm3val1(self) -> Reg<Sm3val1, RW>

Value Register 1

pub const fn sm3fracval2(self) -> Reg<Sm3fracval2, RW>

Fractional Value Register 2

pub const fn sm3val2(self) -> Reg<Sm3val2, RW>

Value Register 2

pub const fn sm3fracval3(self) -> Reg<Sm3fracval3, RW>

Fractional Value Register 3

pub const fn sm3val3(self) -> Reg<Sm3val3, RW>

Value Register 3

pub const fn sm3fracval4(self) -> Reg<Sm3fracval4, RW>

Fractional Value Register 4

pub const fn sm3val4(self) -> Reg<Sm3val4, RW>

Value Register 4

pub const fn sm3fracval5(self) -> Reg<Sm3fracval5, RW>

Fractional Value Register 5

pub const fn sm3val5(self) -> Reg<Sm3val5, RW>

Value Register 5

pub const fn sm3frctrl(self) -> Reg<Sm3frctrl, RW>

Fractional Control Register

pub const fn sm3octrl(self) -> Reg<Sm3octrl, RW>

Output Control Register

pub const fn sm3sts(self) -> Reg<Sm3sts, RW>

Status Register

pub const fn sm3inten(self) -> Reg<Sm3inten, RW>

Interrupt Enable Register

pub const fn sm3dmaen(self) -> Reg<Sm3dmaen, RW>

DMA Enable Register

pub const fn sm3tctrl(self) -> Reg<Sm3tctrl, RW>

Output Trigger Control Register

pub const fn sm3dismap0(self) -> Reg<Sm3dismap0, RW>

Fault Disable Mapping Register 0

pub const fn sm3dtcnt0(self) -> Reg<Sm3dtcnt0, RW>

Deadtime Count Register 0

pub const fn sm3dtcnt1(self) -> Reg<Sm3dtcnt1, RW>

Deadtime Count Register 1

pub const fn sm3captctrla(self) -> Reg<Sm3captctrla, RW>

Capture Control A Register

pub const fn sm3captcompa(self) -> Reg<Sm3captcompa, RW>

Capture Compare A Register

pub const fn sm3captctrlb(self) -> Reg<Sm3captctrlb, RW>

Capture Control B Register

pub const fn sm3captcompb(self) -> Reg<Sm3captcompb, RW>

Capture Compare B Register

pub const fn sm3captctrlx(self) -> Reg<Sm3captctrlx, RW>

Capture Control X Register

pub const fn sm3captcompx(self) -> Reg<Sm3captcompx, RW>

Capture Compare X Register

pub const fn sm3cval0(self) -> Reg<Sm3cval0, R>

Capture Value 0 Register

pub const fn sm3cval0cyc(self) -> Reg<Sm3cval0cyc, R>

Capture Value 0 Cycle Register

pub const fn sm3cval1(self) -> Reg<Sm3cval1, R>

Capture Value 1 Register

pub const fn sm3cval1cyc(self) -> Reg<Sm3cval1cyc, R>

Capture Value 1 Cycle Register

pub const fn sm3cval2(self) -> Reg<Sm3cval2, R>

Capture Value 2 Register

pub const fn sm3cval2cyc(self) -> Reg<Sm3cval2cyc, R>

Capture Value 2 Cycle Register

pub const fn sm3cval3(self) -> Reg<Sm3cval3, R>

Capture Value 3 Register

pub const fn sm3cval3cyc(self) -> Reg<Sm3cval3cyc, R>

Capture Value 3 Cycle Register

pub const fn sm3cval4(self) -> Reg<Sm3cval4, R>

Capture Value 4 Register

pub const fn sm3cval4cyc(self) -> Reg<Sm3cval4cyc, R>

Capture Value 4 Cycle Register

pub const fn sm3cval5(self) -> Reg<Sm3cval5, R>

Capture Value 5 Register

pub const fn sm3cval5cyc(self) -> Reg<Sm3cval5cyc, R>

Capture Value 5 Cycle Register

pub const fn sm3phasedly(self) -> Reg<Sm3phasedly, RW>

Phase Delay Register

pub const fn sm3captfilta(self) -> Reg<Sm3captfilta, RW>

Capture PWM_A Input Filter Register

pub const fn sm3captfiltb(self) -> Reg<Sm3captfiltb, RW>

Capture PWM_B Input Filter Register

pub const fn sm3captfiltx(self) -> Reg<Sm3captfiltx, RW>

Capture PWM_X Input Filter Register

pub const fn outen(self) -> Reg<Outen, RW>

Output Enable Register

pub const fn mask(self) -> Reg<Mask, RW>

Mask Register

pub const fn swcout(self) -> Reg<Swcout, RW>

Software Controlled Output Register

pub const fn dtsrcsel(self) -> Reg<Dtsrcsel, RW>

PWM Source Select Register

pub const fn mctrl(self) -> Reg<Mctrl, RW>

Master Control Register

pub const fn mctrl2(self) -> Reg<Mctrl2, RW>

Master Control 2 Register

pub const fn fctrl0(self) -> Reg<Fctrl0, RW>

Fault Control Register

pub const fn fsts0(self) -> Reg<Fsts0, RW>

Fault Status Register

pub const fn ffilt0(self) -> Reg<Ffilt0, RW>

Fault Filter Register

pub const fn ftst0(self) -> Reg<Ftst0, RW>

Fault Test Register

pub const fn fctrl20(self) -> Reg<Fctrl20, RW>

Fault Control 2 Register

Trait Implementations

impl Clone for Pwm

fn clone(&self) -> Pwm

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Pwm

fn eq(&self, other: &Pwm) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Pwm

impl Eq for Pwm

impl Send for Pwm

impl StructuralPartialEq for Pwm

impl Sync for Pwm