#[repr(transparent)]pub struct Trig0Chain10(pub u32);Expand description
ETC_TRIG Chain 0/1 Register
Tuple Fields§
§0: u32Implementations§
Source§impl Trig0Chain10
impl Trig0Chain10
Sourcepub const fn csel0(&self) -> Trig0Chain10Csel0
pub const fn csel0(&self) -> Trig0Chain10Csel0
ADC channel selection
Sourcepub const fn set_csel0(&mut self, val: Trig0Chain10Csel0)
pub const fn set_csel0(&mut self, val: Trig0Chain10Csel0)
ADC channel selection
Sourcepub const fn hwts0(&self) -> Trig0Chain10Hwts0
pub const fn hwts0(&self) -> Trig0Chain10Hwts0
Segment 0 HWTS ADC hardware trigger selection
Sourcepub const fn set_hwts0(&mut self, val: Trig0Chain10Hwts0)
pub const fn set_hwts0(&mut self, val: Trig0Chain10Hwts0)
Segment 0 HWTS ADC hardware trigger selection
Sourcepub const fn b2b0(&self) -> Trig0Chain10B2b0
pub const fn b2b0(&self) -> Trig0Chain10B2b0
Segment 0 B2B
Sourcepub const fn set_b2b0(&mut self, val: Trig0Chain10B2b0)
pub const fn set_b2b0(&mut self, val: Trig0Chain10B2b0)
Segment 0 B2B
Sourcepub const fn ie0(&self) -> Trig0Chain10Ie0
pub const fn ie0(&self) -> Trig0Chain10Ie0
Segment 0 interrupt enable. (This bit field is meaningful only when IE0_EN is set)
Sourcepub const fn set_ie0(&mut self, val: Trig0Chain10Ie0)
pub const fn set_ie0(&mut self, val: Trig0Chain10Ie0)
Segment 0 interrupt enable. (This bit field is meaningful only when IE0_EN is set)
Sourcepub const fn ie0_en(&self) -> Trig0Chain10Ie0En
pub const fn ie0_en(&self) -> Trig0Chain10Ie0En
IRQ enable of segment 0.
Sourcepub const fn set_ie0_en(&mut self, val: Trig0Chain10Ie0En)
pub const fn set_ie0_en(&mut self, val: Trig0Chain10Ie0En)
IRQ enable of segment 0.
Sourcepub const fn csel1(&self) -> Trig0Chain10Csel1
pub const fn csel1(&self) -> Trig0Chain10Csel1
ADC channel selection
Sourcepub const fn set_csel1(&mut self, val: Trig0Chain10Csel1)
pub const fn set_csel1(&mut self, val: Trig0Chain10Csel1)
ADC channel selection
Sourcepub const fn hwts1(&self) -> Trig0Chain10Hwts1
pub const fn hwts1(&self) -> Trig0Chain10Hwts1
Segment 1 HWTS ADC hardware trigger selection
Sourcepub const fn set_hwts1(&mut self, val: Trig0Chain10Hwts1)
pub const fn set_hwts1(&mut self, val: Trig0Chain10Hwts1)
Segment 1 HWTS ADC hardware trigger selection
Sourcepub const fn b2b1(&self) -> Trig0Chain10B2b1
pub const fn b2b1(&self) -> Trig0Chain10B2b1
Segment 1 B2B
Sourcepub const fn set_b2b1(&mut self, val: Trig0Chain10B2b1)
pub const fn set_b2b1(&mut self, val: Trig0Chain10B2b1)
Segment 1 B2B
Sourcepub const fn ie1(&self) -> Trig0Chain10Ie1
pub const fn ie1(&self) -> Trig0Chain10Ie1
Segment 1 interrupt enable. (This bit field is meaningful only when IE1_EN is set)
Sourcepub const fn set_ie1(&mut self, val: Trig0Chain10Ie1)
pub const fn set_ie1(&mut self, val: Trig0Chain10Ie1)
Segment 1 interrupt enable. (This bit field is meaningful only when IE1_EN is set)
Sourcepub const fn ie1_en(&self) -> Trig0Chain10Ie1En
pub const fn ie1_en(&self) -> Trig0Chain10Ie1En
IRQ enable of segment 1.
Sourcepub const fn set_ie1_en(&mut self, val: Trig0Chain10Ie1En)
pub const fn set_ie1_en(&mut self, val: Trig0Chain10Ie1En)
IRQ enable of segment 1.
Trait Implementations§
Source§impl Clone for Trig0Chain10
impl Clone for Trig0Chain10
Source§fn clone(&self) -> Trig0Chain10
fn clone(&self) -> Trig0Chain10
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more