#[repr(transparent)]pub struct Cs1cdr(pub u32);Expand description
CCM Clock Divider Register
Tuple Fields§
§0: u32Implementations§
Source§impl Cs1cdr
impl Cs1cdr
Sourcepub const fn sai1_clk_podf(&self) -> Sai1ClkPodf
pub const fn sai1_clk_podf(&self) -> Sai1ClkPodf
Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
Sourcepub const fn set_sai1_clk_podf(&mut self, val: Sai1ClkPodf)
pub const fn set_sai1_clk_podf(&mut self, val: Sai1ClkPodf)
Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
Sourcepub const fn sai1_clk_pred(&self) -> Sai1ClkPred
pub const fn sai1_clk_pred(&self) -> Sai1ClkPred
Divider for sai1 clock pred.
Sourcepub const fn set_sai1_clk_pred(&mut self, val: Sai1ClkPred)
pub const fn set_sai1_clk_pred(&mut self, val: Sai1ClkPred)
Divider for sai1 clock pred.
Sourcepub const fn flexio1_clk_pred(&self) -> Flexio1ClkPred
pub const fn flexio1_clk_pred(&self) -> Flexio1ClkPred
Divider for flexio1 clock.
Sourcepub const fn set_flexio1_clk_pred(&mut self, val: Flexio1ClkPred)
pub const fn set_flexio1_clk_pred(&mut self, val: Flexio1ClkPred)
Divider for flexio1 clock.
Sourcepub const fn sai3_clk_podf(&self) -> Sai3ClkPodf
pub const fn sai3_clk_podf(&self) -> Sai3ClkPodf
Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
Sourcepub const fn set_sai3_clk_podf(&mut self, val: Sai3ClkPodf)
pub const fn set_sai3_clk_podf(&mut self, val: Sai3ClkPodf)
Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
Sourcepub const fn sai3_clk_pred(&self) -> Sai3ClkPred
pub const fn sai3_clk_pred(&self) -> Sai3ClkPred
Divider for sai3 clock pred.
Sourcepub const fn set_sai3_clk_pred(&mut self, val: Sai3ClkPred)
pub const fn set_sai3_clk_pred(&mut self, val: Sai3ClkPred)
Divider for sai3 clock pred.
Sourcepub const fn flexio1_clk_podf(&self) -> Flexio1ClkPodf
pub const fn flexio1_clk_podf(&self) -> Flexio1ClkPodf
Divider for flexio1 clock. Divider should be updated when output clock is gated.
Sourcepub const fn set_flexio1_clk_podf(&mut self, val: Flexio1ClkPodf)
pub const fn set_flexio1_clk_podf(&mut self, val: Flexio1ClkPodf)
Divider for flexio1 clock. Divider should be updated when output clock is gated.