#[repr(transparent)]pub struct Cr(pub u32);Expand description
GPT Control Register
Tuple Fields§
§0: u32Implementations§
Source§impl Cr
impl Cr
Sourcepub const fn set_waiten(&mut self, val: Waiten)
pub const fn set_waiten(&mut self, val: Waiten)
GPT Wait Mode enable
Sourcepub const fn set_dozeen(&mut self, val: Dozeen)
pub const fn set_dozeen(&mut self, val: Dozeen)
GPT Doze Mode Enable
Sourcepub const fn set_stopen(&mut self, val: Stopen)
pub const fn set_stopen(&mut self, val: Stopen)
GPT Stop Mode enable
Sourcepub const fn set_clksrc(&mut self, val: Clksrc)
pub const fn set_clksrc(&mut self, val: Clksrc)
Clock Source select
Sourcepub const fn set_en_24m(&mut self, val: En24m)
pub const fn set_en_24m(&mut self, val: En24m)
Enable 24 MHz clock input from crystal
Sourcepub const fn im2(&self) -> Im2
pub const fn im2(&self) -> Im2
IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event
Sourcepub const fn set_im2(&mut self, val: Im2)
pub const fn set_im2(&mut self, val: Im2)
IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event
Sourcepub const fn om3(&self) -> Om3
pub const fn om3(&self) -> Om3
OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode
Sourcepub const fn set_om3(&mut self, val: Om3)
pub const fn set_om3(&mut self, val: Om3)
OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode